LTC2925IGN datasheet(10/20 Pages) LINER

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LTC2925

2925f

CGATE

0.1

µF

CPGTMR

VCC SENSEP SENSEN

VIN

RONB

VIN

RTB1

RTB2

RFA2

SLAVE2

RFB2

RTA2

RTB3

RTA3

RTA1

RONA

RAMPBUF

TRACK1

TRACK2

TRACK3

FB2

GATE

LTC2925

PGTMR

CSDTMR

SDTMR

SCTMR

GND

2925 F08

RAMP

RFA3

SLAVE3

RFB3

DC/DC

OUT

DC/DC

RUN/SS

OUT

FB3

VIN

PGI

RFA1

SLAVE1

RFB1

SUPPLY

MONITOR

DC/DC

RUN/SS

OUT

FB1

FAULT

VIN

STATUS

REMOTE

RST

SD3

SD2

SD1

ful in systems with an external FET. Since the track cell

drives 0.8V on the TRACKx pins, if RTBx is connected di-

rectly to the FET’s source, the TRACKx pin could poten-

tially pull up the FET’s source towards 0.8V when the FET

is off. RAMPBUF blocks this path.

Shutdown Outputs

In some applications it might be necessary to control the

shutdown or RUN/SS pins of the slave supplies. The

LTC2925 may not be able to supply the rated 1mA of cur-

rent from the FB1, FB2, and FB3 pins when VCC is below

2.9V. If the slave power supplies are capable of operating

at low input voltages, use the open-drain SDx outputs to

drive the SHDN or RUN/SS pins of the slave supplies

(Figures 7 and 8). The SDx pins are released when the ON

pin rises above 1.23V, VCC is above the 2.6V undervoltage

lockout condition, and there are no faults latched. The

shutdown timer begins at the same time, and the supplies

begin to ramp up after the shutdown timer cycle com-

pletes. The duration of the timer cycle is configured by a

capacitor tied between SDTMR and GND. The capacitor

voltage is ramped up by a 10

µA current source and the

SDTMR cycle completes when its voltage reaches 1.23V.

Thus, the capacitor, CSDTMR, required for a given shut-

down timer cycle, tSDTMR, is determined from:

SDTMR

123

µ •

The SDx pins pull low again when the ON pin is pulled

below 1.23V and the RAMP pin is below about 100mV.

pulled low, the supplies are latched off, and the FAULT pin

is held low until the fault is cleared by taking the ON pin

below 0.4V.

The PGI pin, which is normally connected to the RST pin

of an external supply monitor, is pulled up with 10

µA

through a schottky diode allowing it to be pulled safely

above VCC. Since, PGTMR pulls up with a 10µA current

source, the capacitor, CPGTMR, required to configure the

power good timeout duration, tPGTMR, is determined from:

PGTMR

123

µ •

If the power good timeout circuit is unused, tie PGTMR low

and float PGI.

The Ramp Buffer

The RAMPBUF pin provides a buffered version of the RAMP

pin voltage that drives the resistive dividers on the TRACKx

pins. When there is no external FET, it provides up to 3mA

to drive the resistors even though the GATE pin only sup-

plies 10

µA (Figure 8). The RAMPBUF pin also proves use-

APPLICATIO S I FOR ATIO

Figure 8. Typical Application Without External FET

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