12

LTC2902

2902f

APPLICATIO S I FOR ATIO

particular output is known, output fall time (10% to 90%)

is estimated using:

demonstrates that the pull-down current is somewhat

linear versus output voltage. Using the 25

estimated to be approximately 40

Ω. Assuming a 150pF

load capacitance, the fall time is about 13.2ns.

Although the outputs are considered to be “open-drain,”

they do have a weak pull-up capability (see COMPX or RST

Pull-Up Current vs V2 curve). Output rise time (10% to

90%) is estimated using:

The on-resistance as a function of the V2 voltage at room

temperature is estimated using:

R

V

610

21

5

•

–

capacitance, the rise time is 86

µs. If the output needs to

pull up faster and/or to a higher voltage, a smaller

external pull-up resistor may be used. Using a 10k pull-

up resistor, the rise time is reduced to 3.3

µs for a 150pF

load capacitance.

The LTC2902-2 has an active pull-up to V2 on the RST

output. The typical performance curve (RST Pull-Up Cur-

rent vs V2 curve) demonstrates that the pull-up current is

mated to be approximately 625

Ω. A 150pF load capaci-

tance makes the rise time about 206ns.

Selecting the Reset Timing Capacitor

The reset time-out period is adjustable in order to accom-

modate a variety of microprocessor applications. The

of this capacitor is determined by:

217 (pF/ms).

Leaving the CRT pin unconnected will generate a mini-

mum reset time-out of approximately 50

µs. Maximum

reset time-out is limited by the largest available low

leakage capacitor. The accuracy of the time-out period will

be affected by capacitor leakage (the nominal charging

current is 2

µA) and capacitor tolerance. A low leakage

ceramic capacitor is recommended.

Tolerance Programming and the RESET Disable

Using the two digital inputs T0 and T1, the user can

program the global supply tolerance for the LTC2902 (5%,

7.5%, 10%, 12.5%). The larger tolerances provide more

headroom by lowering the trip thresholds.

Table 4. Tolerance Programming

T0

T1

TOLERANCE (%)

Low

Low

5

1.210

Low

High

7.5

1.178

High

Low

10

1.146

High

High

12.5

1.113

Under conventional operation, RST and COMPX will go

pin can be pulled low, overriding the reset operation and

forcing the RST pin high. This feature is useful when

determining supply margins under processor control since

the reset command will not be invoked. The RDIS pin is

allowing the pin to be left floating if unused.

drastically reduced. The RST pin may float to undeter-

mined voltages when connected to high impedance (such

as CMOS logic inputs). The addition of a pull-down resis-

tor from RST to ground will provide a path for stray charge

and/or leakage currents. The resistor value should be

small enough to provide effective pull-down without ex-

cessively loading the pull-up circuitry. Too large a value

may not pull down well enough. A 100k resistor from RST

to ground is satisfactory for most applications.