LTC2488IDE datasheet(13/28 Pages) LINER

13 / 28 page

LTC2488

2488f

APPLICATIONS INFORMATION

Data is shifted out of the SDO pin under control of the

serial clock (SCK) (see Figure 3). Whenever ⎯C⎯S is HIGH,

SDO remains high impedance and SCK is ignored.

In order to shift the conversion result out of the device,

⎯C⎯S must ﬁrst be driven LOW. ⎯E⎯O⎯C is seen at the SDO pin

of the device once ⎯C⎯S is pulled LOW. ⎯E⎯O⎯C changes in real

time as a function of the internal oscillator or the clock

applied to the fO pin from HIGH to LOW at the completion

of a conversion. This signal may be used as an interrupt for

an external microcontroller. Bit 23 (⎯E⎯O⎯C) can be captured

on the ﬁrst rising edge of SCK. Bit 22 is shifted out of the

device on the ﬁrst falling edge of SCK. The ﬁnal data bit

(Bit 0) is shifted out on the on the falling edge of the 23rd

SCK and may be latched on the rising edge of the 24th SCK

pulse. On the falling edge of the 24th SCK pulse, SDO goes

HIGH indicating the initiation of a new conversion cycle.

This bit serves as ⎯E⎯O⎯C (Bit 23) for the next conversion

cycle. Table 2 summarizes the output data format.

As long as the voltage on the IN+ and IN– pins remains be-

tween –0.3V and VCC + 0.3V (absolute maximum operating

range) a conversion result is generated for any differential

input voltage VIN from –FS = –0.5 • VREF to +FS = 0.5 •

VREF. For differential input voltages greater than +FS, the

conversion result is clamped to the value corresponding to

+FS + 1LSB. For differential input voltages below –FS, the

conversion result is clamped to the value –FS – 1LSB.

INPUT DATA FORMAT

The LTC2488 serial input word is 8 bits long. The input

bits (SGL, ODD, A2, A1, A0) are used to select the input

channel.

EOC

SCK

(EXTERNAL)

SDI

SDO

2488 F03

CONVERSION

SLEEP

DATA INPUT/OUTPUT

MSB

BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11

SIG

BIT 21

“0”

BIT 22

BIT 23

SGL

ODD

BIT 10

BIT 9

BIT 0

DON'T CARE

Figure 3. Channel Selection and Data Output Timing

Table 2. Output Data Format

Differential Input Voltage

VIN*

Bit 23

⎯E⎯O⎯C

Bit 22

DMY

Bit 21

SIG

Bit 20

MSB

Bit 19

Bit 18

Bit 17

…

Bit 4

LSB

Bits 3 to 0

Always 0

VIN* ≥ 0.5 • VREF**

…

0000

0.5 • VREF** – 1LSB

…

0000

0.25 • VREF**

…

0000

0.25 • VREF** – 1LSB

…

0000

…

0000

–1LSB

…

0000

–0.25 • VREF**

…

0000

–0.25 • VREF** – 1LSB

…

0000

–0.5 • VREF**

…

0000

VIN* < –0.5 • VREF**

…

0000

*The differential input voltage VIN = IN

+ – IN–. **The differential reference voltage VREF = REF+ – REF–.

LTC2488IDE датащи(PDF) 13 Page - Linear Technology

LTC2488IDE датащи(HTML) 13 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

датащи скачать

ссылки URL