LTC2484CDD datasheet(25/40 Pages) LINER

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LTC2484

2484fa

APPLICATIO S I FOR ATIO

then immediately begins outputting data. The data input/

output cycle begins on the first rising edge of SCK and

ends after the 32nd rising edge. The input data is then

shifted in via the SDI pin on the rising edge of SCK

(including the first rising edge) and the output data is

shifted out of the SDO pin on each falling edge of SCK.

The internally generated serial clock is output to the SCK

pin. This signal may be used to shift the conversion result

into external circuitry. EOC can be latched on the first

rising edge of SCK and the last bit of the conversion result

can be latched on the 32nd rising edge of SCK. After the

32nd rising edge, SDO goes HIGH (EOC = 1) indicating a

new conversion is in progress. SCK remains HIGH during

the conversion.

PRESERVING THE CONVERTER ACCURACY

The LTC2484 is designed to reduce as much as possible

the conversion result sensitivity to device decoupling,

PCB layout, antialiasing circuits, line frequency perturba-

tions and so on. Nevertheless, in order to preserve the

24-bit accuracy capability of this part, some simple pre-

cautions are required.

Digital Signal Levels

The LTC2484’s digital interface is easy to use. Its digital

inputs (SDI, FO, CS and SCK in External SCK mode of

operation) accept standard CMOS logic levels and the in-

ternal hysteresis receivers can tolerate edge transition times

as slow as 100

µs. However, some considerations are re-

quired to take advantage of the exceptional accuracy and

low supply current of this converter.

The digital output signals (SDO and SCK in Internal SCK

mode of operation) are less of a concern because they are

not generally active during the conversion state.

While a digital input signal is in the range 0.5V to

(VCC – 0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,

when any one of the digital input signals (SDI, FO, CS

and SCK in External SCK mode of operation) is within

this range, the power supply current may increase even

if the signal in question is at a valid logic level. For

micropower operation, it is recommended to drive all

digital input signals to full CMOS levels [VIL < 0.4V and

VOH > (VCC – 0.4V)].

Figure 10. Internal Serial Clock, CS = 0 Continuous Operation

GS2

GS1

GS0

SPD

SDI*

DON’T CARE

SDO

SCK

(INTERNAL)

LSB

MSB

SIG

BIT 4

BIT 0

BIT 19

BIT 18

BIT 17

BIT 16

BIT 20

BIT 21

BIT 22

EOC

BIT 23

DATA OUTPUT

CONVERSION

2484 F10

VCC

VREF

IN+

IN–

SCK

SDI

SDO

GND

210

INT/EXT CLOCK

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG

INPUT

µF

2.7V TO 5.5V

LTC2484

3-WIRE

SPI INTERFACE

10k

VCC

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