LTC2483 datasheet(13/32 Pages) LINER

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LTC2483

2483f

APPLICATIO S I FOR ATIO

LTC2483 Data Format

After a START condition, the master sends a 7-bit address

followed by a R/W bit. The bit R/W is 1 for a Read request

and 0 for a Write request. If the 7-bit address agrees with

an LTC2483’s address, that device is selected. When the

device is in the conversion state, it does not accept the

request and issues a Not-Acknowledge (NAK) by leaving

SDA HIGH. A write operation will also generate an NAK

signal. If the conversion is complete, it issues an acknowl-

edge (ACK) by pulling SDA LOW.

The output register contains the last conversion result.

After each conversion is completed, the device automati-

cally enters the sleep state where the supply current is

reduced to 1

µA. When the LTC2483 is addressed for a

Read operation, it acknowledges (by pulling SDA LOW)

and acts as a transmitter. The master and receiver can read

up to three bytes from the LTC2483. After a complete Read

operation (3 bytes), the output register is emptied, a new

conversion is initiated, and a following Read request in the

same output phase will be NAKed. The LTC2483 output

data stream is 24 bits long, shifted out on the falling edges

of SCL. The first bit is the conversion result sign bit (SIG),

see Tables 1 and 2. This bit is HIGH if VIN ≥ 0. It is LOW if

VIN <0. The second bit is the most significant bit (MSB) of

the result. The first two bits (SIG and MSB) can be used to

indicate over range conditions. If both bits are HIGH, the

differential input voltage is above +FS and the following 16

bits are set to LOW to indicate an overrange condition. If

both bits are LOW, the input voltage is below –FS and the

following 16 bits are set to HIGH to indicate an underrange

condition. The function of these two bits is summarized in

Table 1. The next 16 bits contain the conversion results in

binary two’s complement format. The remaining six bits

are LOW.

Table 2. LTC2483 Output Data Format

DIFFERENTIAL INPUT VOLTAGE

BIT 23

BIT 22

BIT 21

BIT 20

BIT 19

…

BIT 6

VIN*

SIG

MSB

VIN* ≥ FS**

…

FS** – 1LSB

…

0.5 • FS**

…

0.5 • FS** – 1LSB

…

–1LSB

…

– 0.5 • FS**

…

– 0.5 • FS** – 1LSB

…

– FS**

…

VIN* < –FS**

…

*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • VREF.

Table 1. LTC2483 Status Bits

BIT 23

BIT 22

INPUT RANGE

SIG

MSB

VIN ≥ 0.5 • VREF

≤ VIN < 0.5 • VREF

–0.5 • VREF ≤ VIN < 0V

VIN < – 0.5 • VREF

As long as the voltage on the IN+ and IN– pins is main-

tained within the – 0.3V to (VCC+ 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage VIN from –FS = –0.5 • VREF to +FS

= 0.5 • VREF. For differential input voltages greater than

+FS, the conversion result is clamped to the value corre-

sponding to the +FS + 1LSB. For differential input voltages

below –FS, the conversion result is clamped to the value

corresponding to –FS – 1LSB.

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