LTC2420CS8 datasheet(18/36 Pages) LINER

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LTC2420

into an internal static shift register. The device remains in

the sleep state until the first rising edge of SCK. Data is

shifted out the SDO pin on each falling edge of SCK

enabling external circuitry to latch data on the rising edge

of SCK. EOC can be latched on the first rising edge of SCK.

On the 24th falling edge of SCK, SDO goes HIGH (EOC = 1)

indicating a new conversion has begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 9.

In order to select the internal serial clock timing mode, the

serial clock pin (SCK) must be floating (Hi-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resistor

is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is auto-

matically selected if SCK is not externally driven.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the device is in the sleep state.

When testing EOC, if the conversion is complete (EOC = 0),

the device will exit the sleep state and enter the data output

state if CS remains LOW. In order to prevent the device

from exiting the low power sleep state, CS must be pulled

HIGH before the first rising edge of SCK. In the internal

SCK timing mode, SCK goes HIGH and the device begins

outputting data at time tEOCtest after the falling edge of CS

(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW

during the falling edge of EOC). The value of tEOCtest is 23µs

if the device is using its internal oscillator (F0 = logic LOW

or HIGH). If FO is driven by an external oscillator of

frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled

HIGH before time tEOCtest, the device remains in the sleep

state. The conversion result is held in the internal static

shift register.

If CS remains LOW longer than tEOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data output cycle begins on

this first rising edge of SCK and concludes after the 24th

rising edge. Data is shifted out the SDO pin on each falling

edge of SCK. The internally generated serial clock is output

to the SCK pin. This signal may be used to shift the

SDO

SCK

(INTERNAL)

MSB

EXR

SIG

BIT 0

LSB20

BIT 4

TEST EOC

BIT 19

BIT 18

BIT 20

BIT 21

BIT 22

EOC

BIT 23

SLEEP

DATA OUTPUT

CONVERSION

2420 F09

<tEOCtest

VCC

VREF

SCK

VIN

SDO

GND

VREF

0.1V TO VCC

VIN

–0.12VREF TO 1.12VREF

µF

2.7V TO 5.5V

LTC2420

VCC

10k

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

Hi-Z

VCC

TEST EOC

Figure 9. Internal Serial Clock, Single Cycle Operation

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