LTC2239 datasheet(13/24 Pages) LINER

13 / 24 page

LTC2239

2239fa

APPLICATIO S I FOR ATIO

Single-Ended Input

For cost sensitive applications, the analog inputs can be

driven single-ended. With a single-ended input the har-

monic distortion and INL will degrade, but the SNR and

DNL will remain unchanged. For a single-ended input, AIN+

should be driven with the input signal and AIN– should be

connected to 1.5V or VCM.

Common Mode Bias

For optimal performance the analog inputs should be

driven differentially. Each input should swing

±0.5V for

the 2V range or

±0.25V for the 1V range, around a

common mode voltage of 1.5V. The VCM output pin (Pin

31) may be used to provide the common mode bias level.

VCM can be tied directly to the center tap of a transformer

to set the DC input level or as a reference level to an op amp

differential driver circuit. The VCM pin must be bypassed to

ground close to the ADC with a 2.2

µF or greater capacitor.

Input Drive Impedance

As with all high performance, high speed ADCs, the

dynamic performance of the LTC2239 can be influenced

by the input drive circuitry, particularly the second and

third harmonics. Source impedance and reactance can

influence SFDR. At the falling edge of CLK, the sample-

and-hold circuit will connect the 4pF sampling capacitor to

the input pin and start the sampling period. The sampling

period ends when CLK rises, holding the sampled input on

the sampling capacitor. Ideally the input circuitry should

be fast enough to fully charge the sampling capacitor

during the sampling period 1/(2FENCODE); however, this is

not always possible and the incomplete settling may

degrade the SFDR. The sampling glitch has been designed

to be as linear as possible to minimize the effects of

incomplete settling.

For the best performance, it is recommended to have a

source impedance of 100

Ω or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2239 being driven by an RF

transformer with a center tapped secondary. The second-

ary center tap is DC biased with VCM, setting the ADC input

signal at its optimum DC level. Terminating on the trans-

former secondary is desirable, as this provides a common

mode path for charging glitches caused by the sample and

hold. Figure 3 shows a 1:1 turns ratio transformer. Other

turns ratios can be used if the source impedance seen by

the ADC does not exceed 100

Ω for each ADC input. A

disadvantage of using a transformer is the loss of low

frequency response. Most small RF transformers have

poor performance at frequencies below 1MHz.

Figure 4 demonstrates the use of a differential amplifier to

convert a single ended input signal into a differential input

signal. The advantage of this method is that it provides low

frequency input response; however, the limited gain band-

width of most op amps will limit the SFDR at high input

frequencies.

Ω

0.1

µF

AIN

–

12pF

2.2

µF

VCM

LTC2239

ANALOG

INPUT

0.1

µFT1

1:1

T1 = MA/COM ETC1-1T

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

2239 F03

Figure 4. Differential Drive with an Amplifier

Ω

12pF

2.2

µF

VCM

LTC2239

2239 F04

–

ANALOG

INPUT

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

AIN

–

Figure 3. Single-Ended to Differential Conversion

Using a Transformer

LTC2239 датащи(PDF) 13 Page - Linear Technology

LTC2239 датащи(HTML) 13 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL