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LTC6241CS8 датащи(PDF) 21 Page - Linear Technology

номер детали LTC6241CS8
подробное описание детали  Single/Dual/Quad 18MHz, Low Noise, Rail-to-Rail Output, CMOS Op Amps
PDF  28 Pages
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производитель  LINER [Linear Technology]
домашняя страница  http://www.linear.com
Logo LINER - Linear Technology

LTC6241CS8 датащи(HTML) 21 Page - Linear Technology

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LTC6240/LTC6241/LTC6242
21
624012fc
APPLICATIO S I FOR ATIO
+
–
+
–
BIAS
10M
1
µF
14
15
16
3
2
1
S4
S3
240k
1
µF
OUTPUT
A2
LTC6241HV
A1
LTC6241HV
1
µF
INPUT
10k
8
7
11
S1
S2
9
6
10
R2
10k
R1
10
Ω
NOISE
OFFSET
DRIFT
OPEN-LOOP GAIN
I
= 40nVP-P 0.1Hz TO 10Hz
= 1
µV
= 0.05
µV/°C
R2
10
= 10
= 500pA
+1
GAIN =
9
0.01
µF
Ø1
Ø1
Ø2
Ø2
6241 F09
= 0.1% METAL FILM RESISTOR
= 1% METAL FILM RESISTOR
*
**
= LTC201 QUAD
= LSK389
= LINEAR INTEGRATED SYSTEMS
FREMONT, CA
1
µF
DIV
RSET
LTC1799
V +
74C90
÷ 10
18.5kHz
OUT
74C74
÷ 2
TO
Ø1
POINTS
TO
Ø2
POINTS
QQ
54.2k*
TO LTC201 V+ PIN
5V
5V
–5V
5V
5V
925Hz
TO LTC201 V – PIN
1
µF
898
Ω**
5V
–5V
898
Ω**
LSK389
30.1
Ω
499
Ω**
Figure 9. Ultra Low Noise Chopper Amplifier
to achieve an extraordinarily low noise and low DC drift.
The performance of this circuit is suited for the demand-
ing transducer signal conditioning situations such as high
resolution scales and magnetic search coils.
The LTC1799’s output is divided down to form a 2-phase
925Hz square wave clock. This frequency, harmonically
unrelated to 60Hz, provides excellent immunity to harmonic
beating or mixing effects which could cause instabilities.
S1 and S2 receive complementary drive, causing A1 to
see a chopped version of the input voltage. A1’s square
wave output is synchronously demodulated by S3 and
S4. Because these switches are synchronously driven
with the input chopper, proper amplitude and polarity
information is presented to A2, the DC output amplifier.
This stage integrates the square wave into a DC voltage,
providing the output. The output is divided down (R2 and
R1) and fed back to the input chopper where it serves as
a zero signal reference. Gain, in this case 1000, is set by
the R1-R2 ratio. Because A1 is AC coupled, its DC offset
and drift do not affect the overall circuit offset, resulting
in the extremely low offset and drift noted. The JFETs
have an input RC damper that minimizes offset voltage
contribution due to parasitic switch behavior, resulting in
the 1µV offset specification.



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