LTC4267-3 datasheet(21/32 Pages) LINER

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LTC4267-3

42673f

collector resistor of the optoisolator can be selected for

an increase in bandwidth at the cost of a reduction in

gain of this stage.

Output Transformer Design Considerations

Since the external feedback resistor divider sets the

output voltage, the PD designer has relative freedom in

selecting the transformer turns ratio. The PD designer

can use simple ratios of small integers (i.e. 1:1, 2:1, 3:2)

which yields more freedom in setting the total turns and

mutual inductance and may allow the use of an off the

shelf transformer.

Transformer leakage inductance on either the primary or

secondary causes a voltage spike to occur after the output

switch (Q1 in Figure 11) turns off. The input supply volt-

age plus the secondary-to-primary referred voltage of the

ﬂyback pulse (including leakage spike) must not exceed

the allowed external MOSFET breakdown rating. This spike

is increasingly prominent at higher load currents, where

more stored energy must be dissipated. In some cases,

a “snubber” circuit will be required to avoid overvoltage

breakdown at the MOSFET’s drain node. Application

Note 19 is a good reference for snubber design.

Current Sense Resistor Consideration

The external current sense resistor (RSENSE in Figure 11)

allows the designer to optimize the current limit behavior

for a particular application. As the current sense resistor

is varied from several ohms down to tens of milliohms,

peak swing current goes from a fraction of an ampere to

several amperes. Care must be taken to ensure proper

circuit operation, especially for small current sense resis-

tor values.

Choose RSENSE such that the switching current exercises

the entire range of the ITH/RUN voltage. The nominal volt-

age range is 0.7V to 1.9V and RSENSE can be determined

by experiment. The main loop can be temporarily stabilized

by connecting a large capacitor on the power supply. Apply

the maximum load current allowable at the power sup-

ply output based on the class of the PD. Choose RSENSE

such that ITH/RUN approaches 1.9V. Finally, exercise the

output load current over the entire operating range and

ensure that ITH/RUN voltage remains within the 0.7V to

1.9V range. Layout is critical around the RSENSE resistor.

For example, a 0.020

Ω sense resistor, with one milliohm

(0.001

Ω)ofparasiticresistancewillcausea5%reduction

in peak switch current. The resistance of printed circuit

copper traces cannot necessarily be ignored and good

layout techniques are mandatory.

Programmable Slope Compensation

The LTC4267-3 switching regulator injects a ramping

current through its SENSE pin into an external slope

compensation resistor (RSL in Figure 11). This current

ramp starts at zero after the NGATE pin has been high for

the LTC4267-3’s minimum duty cycle of 6%. The current

rises linearly towards a peak of 5µA at the maximum duty

cycle of 80%, shutting off once the NGATE pin goes low.

A series resistor (RSL) connecting the SENSE pin to the

current sense resistor (RSENSE) develops a ramping volt-

age drop. From the perspective of the LTC4267-3 SENSE

pin, this ramping voltage adds to the voltage across the

sense resistor, effectively reducing the current comparator

threshold in proportion to duty cycle. This stabilizes the

control loop against subharmonic oscillation. The amount

of reduction in the current comparator threshold (∆VSENSE)

can be calculated using the following equation:

∆VSENSE = 5µA • RSL • [(Duty Cycle – 6%)/74%]

Note: The LTC4267-3 enforces 6% < Duty Cycle < 80%.

Designs not needing slope compensation may replace

RSL with a short-circuit.

APPLICATIO S I FOR ATIO

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