LTC4265 datasheet(3/20 Pages) LINER

3 / 20 page

LTC4265

4265f

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to any Absolute Maximum

Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All voltages are with respect to VIN pin unless otherwise noted.

Note 3: Pins with 100V absolute maximum guaranteed for T ≥ 0ºC, otherwise 90V.

Note 4: PWRGD voltage clamps at 14V with respect to VOUT.

Note 5: Input voltage speciﬁcations are deﬁned with respect to LTC4265

pins and meet IEEE 802.3af/at speciﬁcations when the input diode bridge

is included.

The

l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C.

Note 6: Signature resistance is measured via the

ΔV/ΔI method with a

minimum

ΔV of 1V. The LTC4265 signature resistance accounts for the

additional series resistance in the input diode bridge.

Note 7: An invalid signature after the 1st classiﬁcation event is mandated

by IEEE 802.3at standard. See Applications Information.

Note 8: Class accuracy is with respect to the ideal current deﬁned as

1.237/RCLASS and does not include variations in RCLASS resistance.

Note 9: This parameter is assured by design and wafer level testing.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Operating Input Voltage

Signature Range

Classiﬁcation Range

Turn-On Voltage

Undervoltage Lock Out

Overvoltage Lock Out

At GND Pin (Note 5)

1.5

12.5

30.0

9.8

37.2

ON/UVLO Hysteresis Window

4.1

Signature/Class Hysteresis Window

1.4

Reset Threshold

State Machine Reset for 2-event Classiﬁcation

2.57

5.40

SUPPLY CURRENT

Supply Current at 60V

Measured at GND Pin

1.35

Class 0 Current

GND = 17.5V, No RCLASS Resistor

0.40

SIGNATURE

Signature Resistance

1.5V ≤ GND ≤ 9.8V (Note 6)

23.25

kΩ

Invalid Signature Resistance, SHDN Invoked

1.5V ≤ GND ≤ 9.8V, VSHDN = 3V (Note 6)

kΩ

Invalid Signature Resistance During Mark Event (Notes 6, 7)

kΩ

CLASSIFICATION

Class Accuracy

10mA < ICLASS < 40mA, 12.5V < GND < 21V (Note 8, 9)

±3.5

Classiﬁcation Stability Time

GND Pin Step to 17.5V, RCLASS = 30.9, ICLASS Within

3.5% of Ideal Value (Notes 8, 9)

1ms

NORMAL OPERATION

Inrush Current

GND = 54, VOUT = 3V

100

180

Power FET On Resistance

Tested at 600mA into VOUT, GND = 54V

0.70

1.0

Power FET Leakage Current at VOUT

GND = SHDN = VOUT = 57V

1μA

DIGITAL INTERFACE

SHDN Input High Level Voltage

SHDN Input Low Level Voltage

0.45

SHDN Input Resistance

GND = 9.8V, SHDN = 9.65V

100

kΩ

PWRGD, T2PSE Voltage Output Low

Tested at 1mA, GND = 54V. For T2PSE, Must Complete

2-event Classiﬁcation to See Active Low.

0.15

PWRGD, T2PSE Leakage Current

Pin Voltage Pulled 57V, GND = VIN = 0

1μA

PWRGD Voltage Output Low

Tested at 0.5mA, GND = 52V, VOUT = 48V, Output Voltage

is with Respect to VOUT

0.4

PWRGD Voltage Clamp

Tested at 2mA, VOUT = 0V, Voltage with Respect to VOUT

16.5

PWRGD Leakage Current

VPWRGD = 11V, VOUT = VIN = 0V, GND = 54V

1μA

LTC4265 датащи(PDF) 3 Page - Linear Technology

LTC4265 датащи(HTML) 3 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

датащи скачать

ссылки URL