12

LTC1642A

1642af

Overvoltage Protection

The LTC1642A can protect a load from overvoltages by

turning off the pass transistor if the supply voltage ex-

ceeds an adjustable limit, and by triggering a crowbar SCR

if the overvoltage lasts longer than an adjustable time. The

part can also be configured to automatically restart when

the overvoltage clears.

The overvoltage protection circuitry is shown in Figure 8.

The external components comprise a resistor divider

driving the OV pin, timing capacitor C5, NPN emitter

follower Q2, and crowbar SCR Q3. Because the MCR12DC

is not a sensitive-gate device, the optional resistor shunt-

ing the SCR gate to ground is omitted. The internal

components comprise a comparator, 1.22V bandgap ref-

erence, two current sources, and a timer at the CRWBR

output goes high and internal logic turns off Q1 and starts

the timer. This timer has a 0.410V threshold and uses the

CRWBR pin; when CRWBR reaches 0.410V the timer

creases to 1.5mA. Emitter follower Q2 boosts this current

to trigger crowbar SCR Q3. The ramp time

∆t needed to

trip the comparator is:

D1

1N4705

18V

GATE

ON

14

SENSE

15

CRWBR

1

4

FAULT

6

OV

9

16

R2

0.015

Ω

Q1

FDS6630A

GND

LTC1642A

8

RST TMR

3

R6

127k

1%

R5

12.4k

1%

12V

2.5A

1642a F08

R3

100

Ω

R4

330

Ω

C2

0.047

µF

+

C1

0.33

µF

ALL RESISTORS

±5% UNLESS NOTED

RESET TIME = 200ms

CROWBAR DELAY TIME = 90

µs

Q2

2N2222

Q3

MCR12DC

* ADD 220

Ω RESISTOR IF

USING A SENSITIVE-GATE SCR

C5

0.01

µF

Figure 8. Overvoltage Protection Circuitry

Figure 9. Overvoltage Timing (Input Side)

APPLICATIO S I FOR ATIO

100ms/DIV

1642a F09

IN

OV

GATE

OUT

CRWBR

RST TMR

ON

FAULT

20V/DIV

2V/DIV

50V/DIV

20V/DIV

1V/DIV

2V/DIV

20V/DIV

20V/DIV

Once the CRWBR timer trips the LTC1642A latches off:

after the overvoltage clears GATE and FAULT remain at

ground and CRWBR continues sourcing 1.5mA. To restart

the part after the overvoltage clears, hold the ON pin low

for at least 2

µsandthenbringithigh.TheGATEvoltagewill

begin ramping up one system timing cycle later. The part

will restart itself if FAULT and ON are connected.

Figure 9 shows typical waveforms when the divider is

causing the chip to pull the GATE pin to ground and start

the CRWBR timer. At time 2, before the timer’s compara-

tor trips, OV falls below its threshold; the timer resets and

GATE begins charging one system timing cycle later at

time 3. Another overvoltage begins at time 4, and at time

5 the CRWBR timer trips; FAULT goes low and the CRWBR

pin begins sourcing 1.5mA. Even after OV falls below

1.22V at time 6, GATE and FAULT stay low, and CRWBR

continues to source 1.5mA. FAULT goes high when ON

goes low at time 7, and GATE begins charging at time 8,

one RST TMR cycle after FAULT goes high.

Figure 10 shows typical waveforms when the OV divider is

driven from the N-Channel’s output side. Because the

voltage driving the divider collapses after the OV compara-

tor trips, FAULT stays high and CRWBR stays near ground,

which prevents the pin from triggering an SCR. The GATE

voltage begins ramping up after a RST TMR timing cycle.

To disable overvoltage protection completely, tie the OV

and CRWBR pins to GND. For overvoltage protection at the

GATE pin, but without latch off or a crowbar SCR such as

Q3 in Figure 1, tie CRWBR to GND.