LTC1098ACN8 datasheet(27/32 Pages) LINER

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LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

TYPICAL APPLICATIONS

Interfacing to the Parallel Port of the

Intel 8051 Family

The Intel 8051 has been chosen to demonstrate the

interface between the LTC1098(L) and parallel port mi-

croprocessors. Normally the CS, CLK and DIN signals

would be generated on three port lines and the DOUT signal

read on a fourth port line. This works very well. However,

we will demonstrate here an interface with the DIN and

DOUT of the LTC1098(L) tied together as described in the

SERIAL INTERFACE section. This saves one wire.

The 8051 ﬁrst sends the start bit and MUX address to the

LTC1098(L) over the data line connected to P1.2. Then

P1.2 is reconﬁgured as an input (by writing to it a one) and

the 8051 reads back the 8-bit A/D result over the same

data line.

DOUT from LTC1098(L) Stored in 8051 RAM

CLK

DOUT

DIN

LTC1098(L)

ANALOG

INPUTS

P1.4

P1.3

P1.2

8051

MUX ADDRESS

A/D RESULT

10968 TA06

10968 TA07

MSB

LSB

CLK

DATA (DIN/DOUT)

START

ODD/

SIGN

MSBF

MSBF BIT LATCHED

BY LTC1098(L)

LTC1098(L) SENDS A/D RESULT

BACK TO 8051 P1.2

8051 P1.2 OUTPUTS DATA

TO LTC1098(L)

8051 P1.2 RECONFIGURED

AS AN INPUT AFTER THE 4TH RISING

CLK AND BEFORE THE 4TH FALLING CLK

LTC1098(L) TAKES CONTROL OF DATA LINE

ON 4TH FALLING CLK

SGL/

DIFF

10968 TA08

LABEL

MNEMONIC

OPERAND

COMMENTS

LOOP 1

LOOP

MOV

SETB

CLR

MOV

RLC

CLR

MOV

SETB

DJNZ

MOV

CLR

MOV

RLC

SETB

CLR

DJNZ

MOV

SETB

A, #FFH

P1.4

R4, #04

P1.3

P1.2, C

P1.3

R4, LOOP 1

P1, #04

P1.3

R4, #09

C, P1.2

P1.3

R4, LOOP

R2, A

P1.4

DIN word for LTC1098(L)

Make sure CS is high

CS goes low

Load counter

Rotate DIN bit into Carry

CLK goes low

Output DIN bit to LTC1098(L)

CLK goes high

Next bit

Bit 2 becomes an input

CLK goes low

Load counter

Read data bit into Carry

Rotate data bit into Acc.

CLK goes high

CLK goes low

Next bit

Store MSBs in R2

CS goes high

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