AX2000-1CS896B datasheet(98/226 Pages) ACTEL

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Axcelerator Family FPGAs

2- 84

v2.7

Table 2-96 • FIFO Signal Description

Signal

Direction

Description

WCLK

Input

Write clock (active either edge).

FWEN

Input

FIFO write enable. When this signal is asserted, the WD bus data is latched into the

FIFO, and the internal write counters are incremented.

WD[N-1:0]

Input

Write data bus. The value N is dependent on the RAM configuration and can be 1,

2, 4, 9, 18, or 36.

FULL

Output

Active high signal indicating that the FIFO is FULL. When this signal is set,

additional write requests are ignored.

AFULL

Output

Active high signal indicating that the FIFO is AFULL.

AFVAL

Input

8-bit input defining the AFULL value of the FIFO.

RCLK

Input

Read clock (active either edge).

FREN

Input

FIFO read enable.

RD[N-1:0]

Output

Read data bus. The value N is dependent on the RAM configuration and can be 1,

2, 4, 9, 18, or 36.

EMPTY

Output

Empty flag indicating that the FIFO is EMPTY. When this signal is asserted,

attempts to read the FIFO will be ignored.

AEMPTY

Output

Active high signal indicating that the FIFO is AEMPTY.

AEVAL

Input

8-bit input defining the almost-empty value of the FIFO.

PIPE

Input

Sets the pipe option on or off.

CLR

Input

Active high clear input.

DEPTH

Input

Determines the depth of the FIFO and the number of FIFOs to be cascaded.

WIDTH

Input

Determines the width of the dataword / width of the FIFO, and the number of the

FIFOs to be cascaded.

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