A14100A-RQ208C datasheet(34/68 Pages) ACTEL

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A1440A, A14V40A Timing Characteristics (continued)

(Worst-Case Commercial Conditions)

Note:

Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

I/O Module Input Propagation Delays

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

3.3V Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

tINY

Input Data Pad to Y

2.8

3.2

3.6

4.2

5.5

tICKY

Input Reg IOCLK Pad to Y

4.7

5.3

6.0

7.0

9.2

tOCKY

Output Reg IOCLK Pad to Y

4.7

5.3

6.0

7.0

9.2

tICLRY

Input Asynchronous

Clear to Y

4.7

5.3

6.0

7.0

9.2

tOCLRY

Output Asynchronous

Clear to Y

4.7

5.3

6.0

7.0

9.2

Predicted Input Routing Delays1

tIRD1

FO=1 Routing Delay

0.9

1.0

1.1

1.3

1.7

tIRD2

FO=2 Routing Delay

1.2

1.4

1.6

1.8

2.4

tIRD3

FO=3 Routing Delay

1.4

1.6

1.8

2.1

2.8

tIRD4

FO=4 Routing Delay

1.7

1.9

2.2

2.5

3.3

tIRD8

FO=8 Routing Delay

2.8

3.2

3.6

4.2

5.5

I/O Module Sequential Timing

tINH

Input F-F Data Hold

(w.r.t. IOCLK Pad)

0.0

tINSU

Input F-F Data Setup

(w.r.t. IOCLK Pad)

1.5

1.7

2.0

2.3

tIDEH

Input Data Enable Hold

(w.r.t. IOCLK Pad)

0.0

tIDESU

Input Data Enable Setup

(w.r.t. IOCLK Pad)

5.8

6.5

7.5

8.6

tOUTH

Output F-F Data Hold

(w.r.t. IOCLK Pad)

0.7

0.8

0.9

1.0

tOUTSU

Output F-F Data Setup

(w.r.t. IOCLK Pad)

0.7

0.8

0.9

1.0

tODEH

Output Data Enable Hold

(w.r.t. IOCLK Pad)

0.3

0.4

0.5

tODESU

Output Data Enable Setup

(w.r.t. IOCLK Pad)

1.3

1.5

1.7

2.0

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