LT1809CS6 datasheet(16/24 Pages) LINER

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LT1809/LT1810

APPLICATIO S I FOR ATIO

Table 1. LT1809 6-Lead SOT-23 Package

COPPER AREA

BOARD AREA

THERMAL RESISTANCE

TOPSIDE (mm2)

(mm2)

(JUNCTION-TO-AMBIENT)

270

2500

135

°C/W

100

2500

145

°C/W

2500

160

°C/W

2500

200

°C/W

Device is mounted on topside.

Table 2. LT1809/LT1810 SO-8 Package

COPPER AREA

TOPSIDE

BACKSIDE

BOARD AREA

THERMAL RESISTANCE

(mm2)

(JUNCTION-TO-AMBIENT)

1100

2500

°C/W

330

2500

°C/W

2500

°C/W

2500

100

°C/W

2500

105

°C/W

Device is mounted on topside.

Table 3. LT1810 8-Lead MSOP Package

COPPER AREA

TOPSIDE

BACKSIDE

BOARD AREA

THERMAL RESISTANCE

(mm2)

(JUNCTION-TO-AMBIENT)

540

2500

110

°C/W

100

2500

120

°C/W

100

2500

130

°C/W

2500

135

°C/W

2500

140

°C/W

Device is mounted on topside.

Junction temperature TJ is calculated from the ambient

temperature TA and power dissipation PD as follows:

TJ = TA + (PD • θJA)

The power dissipation in the IC is the function of the supply

voltage, output voltage and the load resistance. For a given

supply voltage, the worst-case power dissipation PD(MAX)

occurs at the maximum supply current with the output

voltage at half of either supply voltage (or the maximum

swing is less than 1/2 the supply voltage). PD(MAX) is given

by:

PD(MAX) = (VS • IS(MAX)) + (VS/2)2/RL

Example: An LT1810 in SO-8 mounted on a 2500mm2

area of PC board without any extra heat spreading plane

connected to its V– pin has a thermal resistance of

105

°C/W, θJA. Operating on ±5V supplies with both

amplifiers simultaneously driving 50

Ω loads, the worst-

case power dissipation is given by:

PD(MAX) = 2 • (10 • 25mA) + 2 • (2.5)2/50

= 0.5 + 0.250 = 0.750W

The maximum ambient temperature that the part is al-

lowed to operate is:

TA = TJ – (PD(MAX) • 105°C/W)

= 150

°C – (0.750W • 105°C/W) = 71°C

To operate the device at higher ambient temperature,

connect more metal area to the V – pin to reduce the

thermal resistance of the package as indicated in Table 2.

Input Offset Voltage

The offset voltage will change depending upon which input

stage is active and the maximum offset voltage is guaran-

teed to be less than 3mV. The change of VOS over the entire

input common mode range (CMRR) is less than 2.5mV on

a single 5V and 3V supply.

Input Bias Current

The input bias current polarity depends upon a given input

common voltage at whichever input stage is operating.

When the PNP input stage is active, the input bias currents

flow out of the input pins and flow into the input pins when

the NPN input stage is activated. Because the input offset

current is less than the input bias current, matching the

source resistances at the input pin will reduce total offset

error.

Output

The LT1809/LT1810 can deliver a large output current,

so the short-circuit current limit is set around 90mA to

prevent damage to the device. Attention must be paid to

keep the junction temperature of the IC below the abso-

lute maximum rating of 150

°C (refer to the Power Dissi-

pation section) when the output is continuously short

circuited. The output of the amplifier has reverse-biased

diodes connected to each supply. If the output is forced

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