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11/12/01

Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability

indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to

workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the

Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.

TP5335

Advanced DMOS Technology

These enhancement-mode (normally-off) transistors utilize a

vertical DMOS structure and Supertex’s well-proven silicon-gate

manufacturing process. This combination produces devices with

the power handling capabilities of bipolar transistors and with the

high input impedance and positive temperature coefficient inher-

ent in MOS devices. Characteristic of all MOS structures, these

devices are free from thermal runaway and thermally-induced

secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide range

of switching and amplifying applications where high breakdown

voltage, high input impedance, low input capacitance, and fast

switching speeds are desired.

Note: See Package Outline section for dimensions.

Package Options

Features

Free from secondary breakdown

Low power drive requirement

Ease of paralleling

Low C

Excellent thermal stability

Integral Source-Drain diode

High input impedance and high gain

Complementary N- and P-channel devices

Applications

Logic level interfaces – ideal for TTL and CMOS

Solid state relays

Analog switches

Power Management

Telecom switches

TO-236AB

(SOT-23)

top view

Gate

Source

Drain

P-Channel Enhancement-Mode

Vertical DMOS FETs

Low Threshold

Absolute Maximum Ratings

Drain-to-Source Voltage

Drain-to-Gate Voltage

BV

DGS

Gate-to-Source Voltage

± 20V

Operating and Storage Temperature

-55°C to +150°C

Soldering Temperature*

300°C

Product Objective Specification

(max)

(max)

TO-236AB*

Wafer

-350V

30Ω

-2.4V

TP5335K1

TP5335NW

*Same as SOT-23. All units shipped on 3,000 piece carrier tape reels.

Ordering Information

Order Number/Package

Product marking for SOT-23

Where *=2-week alpha date code

P3S

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