F75111 datasheet(11/45 Pages) FINTEK

11 / 45 page

July, 2007

V0.27P

- 9 -

F75111

Start By

Master

011

Ack

111

R/W

Ack

111

SCL

SDA

Frame 2

Internal Index Register Byte

Frame 1

Serial Bus Address Byte

Figure 2. Serial Bus Write to Internal Address Register Only

Stop by

Master

Start By

Master

011

Ack

Master

R/W

Ack

111

SCL

SDA

Frame 2

Internal Index Register Byte

Frame 1

Serial Bus Address Byte

Figure 3. Serial Bus Read from Internal Address Register

Stop by

Master

7. Registers Description

7.1 Configuration and Control Register – Index 01h

Power-on default [7:0] =0000_1000b

Bit

Name

R/W

PWR

Description

INIT

R/W

VSB3V

Software reset for all registers including Test Mode registers. Users use

only.

Reserved

R/W

VSB3V

EN_WDT10

R/W

VSB3V

Enable Reset Out. If set to 1, enable WDTOUT10# output. Default is

disable.

Reserved

R/W

VSB3V

Reserved

R/W

VSB3V

Reserved

R/W

VSB3V

SMART_POW

R_MANAGEM

ENT

R/W

VSB3V

Set this bit to 1 will enable auto power down mode, when all function are

idle then 20ms the chip will auto power down, it will wakeup when GPIO

state change or read write register

SOFT_POWR_

DOWN

R/W

VSB3V

Set this bit to 1 will power down all of the analog block and stop internal

clock, write 0 to clear this bit or when GPIO state change will auto clear

this bit to 0.

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