LT1073

10

In Figure 9, the input is negative while the output is

positive. In this configuration, the magnitude of the input

voltage can be higher or lower than the output voltage. A

level shift, provided by the PNP transistor, supplies proper

polarity feedback information to the regulator.

The LT1073 switch can be programmed to turn off at a set

switch current, a feature not found on competing devices.

This enables the input to vary over a wide range without

exceeding the maximum switch rating or saturating the

inductor. Consider the case where analysis shows the

LT1073 must operate at an 800mA peak switch current

will rise to 1.6A, exceeding the maximum switch current

rating. With the proper resistor (see the “Maximum Switch

rent will be limited to 800mA, even if the input voltage

increases. The LT1073 does this by sampling a small

fraction of the switch current and passing this current

cycle. Propagation delay through this loop is about 2

µs.

the device goes into continuous mode operation. This

occurs in step-up mode when

APPLICATIO S I FOR ATIO

Figure 10. No Current Limit Causes

Large Inductor Current Build-Up

Figure 11. Current Limit Keeps Inductor Current Under Control

VV

VV

DC

OUT

DIODE

IN

SW

+

<

––

1

1

When the input and output voltages satisfy this relation-

ship, inductor current does not go to zero during the

switch OFF time. When the switch turns on again, the

current ramp starts from the nonzero current level in the

inductor just prior to switch turn-on. As shown in

Figure 10, the inductor current increases to a high level

before the comparator turns off the oscillator. This high

current can cause excessive output ripple and requires

feature, however, the switch current turns off at a pro-

grammed level as shown in Figure 11, keeping output

ripple to a minimum.

Using the Gain Block

The gain block (GB) on the LT1073 can be used as an error

amplifier, low-battery detector or linear post-regulator.

The gain block itself is a very simple PNP input op amp with

an open-collector NPN output. The (–) input of the gain

block is tied internally to the 212mV reference. The (+)

input comes out on the SET pin.

Arrangement of the gain block as a low battery detector is

straightforward. Figure 12 shows hookup. R1 and R2 need

only be low enough in value so that the bias current of the

SET input does not cause large errors. 100k

Ω for R2 is

adequate.

can be reduced significantly by placing the gain block in

front of the FB input as shown in Figure 13. This effectively

reduces the comparator hysteresis by the gain of the gain

block. Output ripple can be reduced to just a few millivolts

using this technique. Ripple reduction works with step-

down or inverting modes as well.

1073 F10

ON

OFF

SWITCH

PROGRAMMED CURRENT LIMIT

1073 F11

ON

OFF

SWITCH