TAS5708 datasheet(16/56 Pages) TI

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ERROR REPORTING

DEVICE PROTECTION SYSTEM

Overcurrent (OC) Protection

Overtemperature Protection

Undervoltage Protection (UVP) and Overvoltage Protection (OVP)

SERIAL DATA INTERFACE

CLOCK, AUTO DETECTION, and PLL

TAS5708

SLOS570 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

Any fault resulting in device shutdown is signaled by the FAULT pin going low (see Table 1). A sticky version of

this pin is available on D1 of register 0X02.

Table 1. FAULT Output States

FAULT

DESCRIPTION

Overcurrent (OC) ERROR

No faults (normal operation)

The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs,

which protects against shorts across the load, to GND, or to PVCC. The protection system triggers a latching

shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state and FAULT being asserted

low. The device returns to normal operation once the fault condition (i.e., a short circuit on the output) is

removed. Current limiting and overcurrent protection are not independent for half-bridges. That is, if the

bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut

down.

The TAS5708 has an over-temperature protection system. If the device junction temperature exceeds 150°C

(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the

high-impedance (Hi-Z) state. The TAS5708 recovers automatically once the temperature drops approximately

15°.

THE UVP circuits of the TAS5708 fully protect the device in any power-up/down and brownout situation. The

UVP engages if PVCC_X = AVCC drops below 8.4-V (typical) and disengages when PVCC_X = AVCC exceeds

8.5-V. The OVP circuits protect aganist voltage spikes and engage when PVCC_X = AVCC exceeds 27.5-V

(typical). The OVP circuits disengage when PVCC_X = AVCC drops below 27.2-V. When the protection circuits

engage, all half-bridge outputs are immediately placed in the high-impedance (Hi-Z) state.

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5708 DAP accepts serial data in

16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.

The TAS5708 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)

supports all the sample rates and MCLK rates that are defined in the clock control register.

The TAS5708 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×

fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section

uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the

internal clock (DCLK) running at 512 times the PWM switching frequency.

The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock

rates as defined in the clock control register.

TAS5708 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect

changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute)

and then force PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the

system will auto detect the new rate and revert to normal operation. During this process, the default volume will

be restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back

slowly (also called soft unmute) as defined in volume register (0X0E).

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