ATSAM3308B datasheet(20/27 Pages) ATMEL

номер детали	ATSAM3308B

подробное описание детали	Audio Processing

PDF	27 Pages

Scroll/Zoom	100%

производитель	ATMEL [ATMEL Corporation]

домашняя страница	http://www.atmel.com

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6090D–DRMSD–12-Feb-07

ATSAM3308B

Note:

1. A built-in PLL multiplies the crystal clock frequency by 4 for internal use. pLCK is the period of the internal clock generated by

PLL. p

LCK = tCK/4. Typical value with crystal 12.288 MHz is pLCK = 20 ns.

2. Memory access time should be lower than tACE min. Typical value with crystal 12.288 MHz is 80 ns.

Figure 10-9.

External RAM/Flash Write Timing

Table 10-4.

External Memory Parameters

Symbol

Parameter

Min

Typ

Max

Unit

tRC

Read cycle time

5 * pLCK

-ns

CSOE

Chip select low/address valid to WOE low

2 * p

LCK - 5

2 * p

LCK + 5

tPOE

Output enable pulse width

3 * pLCK

-ns

tACE

Chip select/address access time

4.5 * pLCK - 10

Output enable access time

2.5 * p

LCK - 10

tDF

Chip select or WOE high to input data Hi-Z

2 * pLCK - 5

tWC

tCSWE

tWP

tDW

tDH

WA0 - WA21

WD0 - WD15

WCS1

WWE

WOE

WCS0

Table 10-5.

External Flash Timing Parameters

Symbol

Parameter

Min

Typ

Max

Unit

Write cycle time

5 * p

LCK

-ns

tCSWE

Write enable low from CS or Address or WOE

2 * pLCK - 5

2 * pLCK + 5

Write pulse width

2.5 * p

LCK

-ns

Data out setup time

2.5 * p

LCK - 5

tDH

Data out hold time

0.5 * pLCK

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