AT88SC0104C datasheet(25/58 Pages) ATMEL

25 / 58 page

5210B–SMIC–11/08

AT88SC0104/0204/0404/0808/1616/3216/6416/12816/25616C

Protocol Selection

CryptoMemory supports two application areas with different communication protocols: a 2-wire

serial communication for embedded applications and an ISO 7816 asynchronous T=0 smart

card interface. The power-up sequence of CryptoMemory determines what mode it shall oper-

ate in. A brief description of each of these modes follows.

6.0.1

Synchronous Mode for Embedded Applications

The 2-wire serial interface is used for fast and efficient communication with logic and controllers.

The synchronous mode is the default after powering up V

CC due to the internal and/or external

pull-up on RST. For embedded applications using CryptoMemory in standard plastic packages

RST is not bonded out and this is the only communication protocol.

Power-up V

CC, RST goes high also.

After stable V

CC, apply 5 pulses CLK-SCL

CLK-SCL and I/O-SDA may then be driven.

Figure 6-1.

Power Up Sequence for 2-Wire Mode

The asynchronous mode is selected when RST is low on a rising edge of CLK. Once the asyn-

chronous mode has been selected, it is not possible to return to the synchronous mode other

than by powering the device off and on again.

6.0.2

Asynchronous Mode for Smart Card Applications

The asynchronous T=0 protocol defined by ISO 7816-3 is used for compatibility with industry

standard smart card readers. Selecting this mode requires the following power-up sequence,

which complies with ISO 7816-3 for a cold reset in smart card applications.

•Power up V

CC; RST, IO-SDA and CLK-SCL are low

• Set I/O-SDA in receive mode

• Provide a clock signal to CLK-SCL

• RST goes high after 400 clock cycles.

The device will respond with a 64-bit ATR code, including historical bytes to indicate the memory

density within the CryptoMemory family.

The 64-bit ATR code comes from a register that contains the characters shown in Table 6-1 on

page 23 and Table 6-2 on page 23. The historical bytes (T1, T2, T3) show the density of the

CryptoMemory device. This register may be modified during personalization but is locked when

the PER fuse is blown. Care must be taken to respect the applicable standards defining the ATR

Vcc

I/O-SDA

RST

CLK-SCL

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