DP83848M datasheet(21/80 Pages) NSC

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10th clock so that an attached device can sample the data

every 10 clocks.

RMII mode requires a 50 MHz oscillator be connected to

the device X1 pin. A 50 MHz crystal is not supported.

To tolerate potential frequency differences between the 50

MHz reference clock and the recovered receive clock, the

receive RMII function includes a programmable elasticity

buffer. The elasticity buffer is programmable to minimize

propagation delay based on expected packet size and

clock accuracy. This allows for supporting a range of

packet sizes including jumbo frames.

The elasticity buffer will force Frame Check Sequence

errors for packets which overrun or underrun the FIFO.

Underrun and Overrun conditions can be reported in the

RMII and Bypass Register (RBR). The following table indi-

cates how to program the elasticity buffer fifo (in 4-bit

increments) based on expected max packet size and

clock accuracy. It assumes both clocks (RMII Reference

clock and far-end Transmitter clock) have the same accu-

racy.

3.3 802.3u MII Serial Management Interface

3.3.1 Serial Management Register Access

The serial management MII specification defines a set of

thirty-two 16-bit status and control registers that are

accessible through the management interface pins MDC

and MDIO. The DP83848M implements all the required

MII registers as well as several optional registers. These

registers are fully described in Section 7.0. A description

of the serial management access protocol follows.

3.3.2 Serial Management Access Protocol

The serial control interface consists of two pins, Manage-

ment Data Clock (MDC) and Management Data Input/Out-

put (MDIO). MDC has a maximum clock rate of 25 MHz

and no minimum rate. The MDIO line is bi-directional and

may be shared by up to 32 devices. The MDIO frame for-

mat is shown below in Table 5.

The MDIO pin requires a pull-up resistor (1.5 k

Ω) which,

during IDLE and turnaround, will pull MDIO high. In order

to initialize the MDIO interface, the station management

entity sends a sequence of 32 contiguous logic ones on

MDIO to provide the DP83848M with a sequence that can

be used to establish synchronization. This preamble may

be generated either by driving MDIO high for 32 consecu-

tive MDC clock cycles, or by simply allowing the MDIO

pull-up resistor to pull the MDIO pin high during which

time 32 MDC clock cycles are provided. In addition, 32

MDC clock cycles should be used to re-sync the device if

an invalid start, opcode, or turnaround bit is detected.

The DP83848M waits until it has received this preamble

sequence before responding to any other transaction.

Once the DP83848M serial management port has been

initialized no further preamble sequencing is required until

after a power-on/reset, invalid Start, invalid Opcode, or

invalid turnaround bit has occurred.

The Start code is indicated by a <01> pattern. This

assures the MDIO line transitions from the default idle line

state.

Turnaround is defined as an idle bit time inserted between

the Register Address field and the Data field. To avoid

contention during a read transaction, no device shall

actively drive the MDIO signal during the first bit of Turn-

around. The addressed DP83848M drives the MDIO with

a zero for the second bit of turnaround and follows this

with the required data. Figure 4 shows the timing relation-

ship between MDC and the MDIO as driven/received by

the Station (STA) and the DP83848M (PHY) for a typical

For write transactions, the station management entity

writes data to the addressed DP83848M thus eliminating

the requirement for MDIO Turnaround. The Turnaround

time is filled by the management entity by inserting <10>.

Figure 5 shows the timing relationship for a typical MII

Table 4. Supported packet sizes at +/-50ppm +/-100ppm for each clock

Start Threshold

RBR[1:0]

Latency Tolerance

Recommended Packet Size

at +/- 50ppm

Recommended Packet Size

at +/- 100ppm

1 (4-bits)

2 bits

2400 bytes

1200 bytes

2 (8-bits)

6 bits

7200 bytes

3600 bytes

3 (12-bits)

10 bits

12000 bytes

6000 bytes

0 (16-bits)

14 bits

16800 bytes

8400 bytes

Table 5. Typical MDIO Frame Format

MII Management

Serial Protocol

Read Operation

Write Operation

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