9202 datasheet(129/175 Pages) STMICROELECTRONICS

129 / 175 page

129/175

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

Port Configuration Registers (PCR)

Each Port has a set of Port Configuration Regis-

ters (PCR) used for configuration. The contents of

the registers can be accessed by the MCU through

normal READ/WRITE bus cycles at the addresses

given in Table 84. The addresses in Table 84 are

the offsets in hexadecimal from the base of the

CSIOP register.

The pins of a port are individually configurable and

each bit in the register controls its respective pin.

For example, Bit 0 in a register refers to Bit 0 of its

port. The three Port Configuration Registers

(PCR), shown in Table 94, are used for setting the

Port configurations. The default Power-up state for

each register in Table 94 is 00h.

Control Register. Any bit reset to '0' in the Con-

trol Register sets the corresponding port pin to

MCU I/O Mode, and a '1' sets it to Address Out

Mode. The default mode is MCU I/O. Only Ports A

and B have an associated Control Register.

Direction Register. The Direction Register, in

conjunction with the output enable (except for Port

D), controls the direction of data flow in the I/O

Ports. Any bit set to '1' in the Direction Register

causes the corresponding pin to be an output, and

any bit set to '0' causes it to be an input. The de-

fault mode for all port pins is input.

Figure 65, page 131 and Figure 66, page 132

show the Port Architecture diagrams for Ports A/B

and C, respectively. The direction of data flow for

Ports A, B, and C are controlled not only by the di-

rection register, but also by the output enable

product term from the PLD AND Array. If the out-

put enable product term is not active, the Direction

An example of a configuration for a Port with the

three least significant bits set to output and the re-

mainder set to input is shown in Table 97. Since

Port D only contains two pins (shown in Figure 68),

the Direction Register for Port D has only two bits

active.

Drive Select Register. The Drive Select Register

configures the pin driver as Open Drain or CMOS

for some port pins, and controls the slew rate for

the other port pins. An external pull-up resistor

should be used for pins configured as Open Drain.

A pin can be configured as Open Drain if its corre-

sponding bit in the Drive Select Register is set to a

'1.' The default pin drive is CMOS.

Note: The slew rate is a measurement of the rise

and fall times of an output. A higher slew rate

means a faster output response and may create

more electrical noise. A pin operates in a high slew

rate when the corresponding bit in the Drive Reg-

ister is set to '1.' The default rate is slow slew.

Table 98, page 130 shows the Drive Register for

Ports A, B, C, and D. It summarizes which pins can

be configured as Open Drain outputs and which

pins the slew rate can be set for.

Table 94. Port Configuration Registers (PCR)

Note: 1. See Table 98 for Drive Register Bit definition.

Table 95. Port Pin Direction Control, Output

Enable P.T. Not Defined

Table 96. Port Pin Direction Control, Output

Enable P.T. Defined

Table 97. Port Direction Assignment Example

Port

MCU Access

Control

A,B

WRITE/READ

Direction

A,B,C,D

WRITE/READ

Drive Select(1)

A,B,C,D

WRITE/READ

Direction Register Bit

Port Pin Mode

Input

Output

Direction

Output Enable

P.T.

Port Pin Mode

Input

Output

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

9202 датащи(PDF) 129 Page - STMicroelectronics

9202 датащи(HTML) 129 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL