9202 datasheet(119/175 Pages) STMICROELECTRONICS

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UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

PLDS

The PLDs bring programmable logic functionality

to the uPSD. After specifying the logic for the

PLDs in PSDsoft Express, the logic is pro-

grammed into the device and available upon Pow-

er-up.

Table 89. DPLD and CPLD Inputs

Note: 1. These inputs are not available in the 52-pin package.

The PSD MODULE contains two PLDs: the De-

code PLD (DPLD), and the Complex PLD (CPLD).

The PLDs are briefly discussed in the next few

paragraphs, and in more detail in the section enti-

tled “Decode PLD (DPLD),” page 121, and the

section entitled “Complex PLD (CPLD),” page 122.

Figure 58 shows the configuration of the PLDs.

The DPLD performs address decoding for Select

signals for PSD MODULE components, such as

memory, registers, and I/O ports.

The CPLD can be used for logic functions, such as

loadable counters and shift registers, state ma-

chines, and encoding and decoding logic. These

logic functions can be constructed using the Out-

put Macrocells (OMC), Input Macrocells (IMC),

and the AND Array. The CPLD can also be used

to generate External Chip Select (ECS1-ECS2)

signals.

The AND Array is used to form product terms.

These product terms are specified using PSDsoft.

The PLD input signals consist of internal MCU sig-

nals and external inputs from the I/O ports. The in-

put signals are shown in Table 89.

The Turbo Bit in PSD MODULE

The PLDs can minimize power consumption by

switching off when inputs remain unchanged for

an extended time of about 70ns. Resetting the

Turbo Bit to '0' (Bit 3 of PMMR0) automatically

places the PLDs into standby if no inputs are

changing. Turning the Turbo Mode off increases

propagation delays while reducing power con-

sumption. See the section entitled “POWER MAN-

AGEMENT,” page 135, on how to set the Turbo

Bit.

Additionally, five bits are available in PMMR2 to

block MCU control signals from entering the PLDs.

This reduces power consumption and can be used

only when these MCU control signals are not used

in PLD logic equations.

Each of the two PLDs has unique characteristics

suited for its applications. They are described in

the following sections.

Input Source

Input Name

Number

Signals

MCU Address Bus

A15-A0

MCU Control Signals

PSEN, RD, WR,

ALE

RESET

RST

Power-down

PDN

Port A Input

Macrocells(1)

PA7-PA0

Port B Input

Macrocells

PB7-PB0

Port C Input

Macrocells

PC2-4, PC7

Port D Inputs

PD2-PD1

Page Register

PGR7-PGR0

Macrocell AB

Feedback

MCELLAB.FB7-

FB0

Macrocell BC

Feedback

MCELLBC.FB7-

FB0

Flash memory

Program Status Bit

Ready/Busy

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