9202 datasheet(105/175 Pages) STMICROELECTRONICS

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UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET

Table 84 shows the offset addresses to the PSD

MODULE registers relative to the CSIOP base ad-

dress. The CSIOP space is the 256 bytes of ad-

dress that is allocated by the user to the internal

PSD MODULE registers. Table 84 provides brief

descriptions of the registers in CSIOP space. The

following section gives a more detailed descrip-

tion.

Table 84. Register Address Offset

Note: 1. Other registers that are not part of the I/O ports.

Port A

Port B

Port C

Port D

Other(1)

Description

Data In

Reads Port pin as input, MCU I/O Input Mode

Control

Selects mode between MCU I/O or Address Out

Data Out

Stores data for output to Port pins, MCU I/O

Output Mode

Direction

Configures Port pin as input or output

Drive Select

Configures Port pins as either CMOS or Open

Drain on some pins, while selecting high slew

rate on other pins.

Input Macrocell

Reads Input Macrocells

Enable Out

Reads the status of the output enable to the I/O

Port driver

Output Macrocells

READ – reads output of macrocells AB

WRITE – loads macrocell flip-flops

Output Macrocells

READ – reads output of macrocells BC

WRITE – loads macrocell flip-flops

Mask Macrocells AB

Blocks writing to the Output Macrocells AB

Mask Macrocells BC

Blocks writing to the Output Macrocells BC

Primary Flash

Protection

Read-only – Primary Flash Sector Protection

Secondary Flash

memory Protection

Read-only – PSD MODULE Security and

Secondary Flash memory Sector Protection

PMMR0

Power Management Register 0

PMMR2

Power Management Register 2

Page

Page Register

Places PSD MODULE memory areas in

Program and/or Data space on an individual

basis.

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