ACS8525P datasheet(13/112 Pages) SEMTECH

13 / 112 page

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.01/August 2005 © Semtech Corp.

Page 13

www.semtech.com

ACS8525 LC/P

device in the JTAG scan chain, the implementation should be

such that a logic change caused by the action of the interrupt

on the TDI input should not effect the operation when JTAG is

not active.

External Protection Switching Mode-SRCSW pin

External Protection Switching mode, for fast switching

between inputs SEC1 or SEC2, can be triggered directly

from the dedicated pin SRCSW, once the mode has been

initialized.

The mode is initialized by either holding SRCSW pin High

during reset (SRCSW must remain High for at least a

further 251 ms after PORB has gone High - see following

Note), or by writing to Reg. 48 Bit 4. After External

Protection Switching mode has been initialized, the value

on this pin directly selects either SEC1 (SRCSW High) or

SEC2 (SRCSW Low). If this mode is activated at reset by

pulling the SRCSW pin High, then it configures the default

frequency tolerance of SEC1 and SEC2 to ±80 ppm

(Reg. 41 and Reg. 42), as opposed to the normal

frequency tolerance of ±9.2 ppm. These registers can be

subsequently set by external software, if required.

Note...The 251 ms comprises 250 ms allowance for the

internal reset to be removed plus 1 ms allowance for APLLs to

start-up and become stable.

The control of TTL or DIFF selection for inputs SEC1 and

SEC2 is independently determined by the priority values

of the TTL inputs; if the programmed priority of SEC1 TTL

is 0, then SEC1 DIFF is available for selection by SRCSW

pin; similarly, if SEC2 TTL is 0 priority, SEC2 DIFF is

available for selection by SRCSW pin (See Reg. 19 and 1A

cnfg_ref_selection_priority and Figure 4).

Figure 4 SEC1 and SEC2 Switching

When external protection switching is enabled, the device

will operate as a simple switch. All clock monitoring is

disabled and the DPLL will simply be forced to try to lock

on to the indicated reference source. Consequently the

device will always indicate “Locked” state in the operating

mode register (Reg. 09, Bits 2:0).

Output Clock Phase Continuity on Source

Switchover

If either PBO is selected on (default), or, if DPLL frequency

limit set to less than ±30 ppm (±9.2 ppm default), the

device will always comply with GR-1244-CORE[13]

specifications for Stratum 3 (max rate of phase change of

81 ns/1.326 ms), for all input frequencies.

A well designed system would have Master and Slave

clock from the clock sync cards aligned to within a few

nanoseconds. In which case a complete system using the

Semtech SETS clock card parts (ACS8530, ACS8520 or

ACS8510) and this Line Card part would be fully

compliant to GR-1244-CORE[13] specifications under all

conditions due to the low frequency range and bandwidth

set at the clock card end. These parts and the ACS8525

LC/P also allow easy frame sync (8 kHz) alignment both at

the clock card and at the Line Card end through the use

of dedicated frame sync (8 kHz) inputs, in addition to the

main clock inputs.

Forcing of the Operating Mode of the Device

The Selector can force the following Operating modes,

(cnfg_operating_mode, Reg. 32):

Auto

Free-run

Holdover

Locked

Lost-phase

Pre-locked

Pre-locked2

See “Operating Modes (States) of the Device” on page 30.

Phase Locked Loops (PLLs)

PLL Overview

Figure 1 shows the PLL circuitry to comprise two Digital

PLLs (DPLL1 and DPLL2), two output multiplying and

filtering Analog PLLs (APLL1 and APLL2), output

frequency dividers in an Output Port Frequency Selection

block, a synthesis block, multiplexers MUX1 and MUX2,

and a feedback Analog PLL (APLL3). These functional

blocks, and their interconnections are highly configurable,

SEC1 TTL Priority >0

SEC2 TTL Priority >0

SEC1 TTL

SEC1 DIFF

DPLL1

SRCSW

SEC2 TTL

SEC2 DIFF

F8525D_006secSwitch_01

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