AT89C51ED2-RDTUM datasheet(12/137 Pages) ATMEL

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4235K–8051–05/08

AT89C51RD2/ED2

I/O

P1.7: Input/Output:

I/O

CEX4: Capture/Compare External I/O for PCA module 4

I/O

MOSI: SPI Master Output Slave Input line

When SPI is in master mode, MOSI outputs data to the slave peripheral.

When SPI is in slave mode, MOSI receives data from the master

controller.

XTALA1

XTALA 1: Input to the inverting oscillator amplifier and input to the

internal clock generator circuits.

XTALA2

XTALA 2: Output from the inverting oscillator amplifier

P2.0 - P2.7

24 - 31

18 - 25

54, 55,

56, 58,

59, 61,

64, 65

43, 44,

45, 47,

48, 50,

53, 54

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2

pins that have 1s written to them are pulled high by the internal pull-ups

and can be used as inputs. As inputs, Port 2 pins that are externally

pulled low will source current because of the internal pull-ups. Port 2

emits the high-order address byte during fetches from external program

memory and during accesses to external data memory that use 16-bit

addresses (MOVX @DPTR).In this application, it uses strong internal

pull-ups emitting 1s. During accesses to external data memory that use

8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.

P3.0 - P3.7

11,

13 - 19

7 - 13

34, 39,

40, 41,

42, 43,

45, 47

25, 28,

29, 30,

31, 32,

34, 36

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3

pins that have 1s written to them are pulled high by the internal pull-ups

and can be used as inputs. As inputs, Port 3 pins that are externally

pulled low will source current because of the internal pull-ups. Port 3 also

serves the special features of the 80C51 family, as listed below.

RXD (P3.0): Serial input port

TXD (P3.1): Serial output port

INT0 (P3.2): External interrupt 0

INT1 (P3.3): External interrupt 1

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

P4.0 - P4.7

20, 24,

26, 44,

46, 50,

53, 57

11, 15,

17,33,

35,39,

42, 46

I/O

Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3

pins that have 1s written to them are pulled high by the internal pull-ups

and can be used as inputs. As inputs, Port 3 pins that are externally

pulled low will source current because of the internal pull-ups.

P5.0 - P5.7

60, 62,

63, 7, 8,

10, 13, 16

49, 51,

52, 62,

63, 1, 4, 7

I/O

Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3

pins that have 1s written to them are pulled high by the internal pull-ups

and can be used as inputs. As inputs, Port 3 pins that are externally

pulled low will source current because of the internal pull-ups.

RST

Reset: A high on this pin for two machine cycles while the oscillator is

running, resets the device. An internal diffused resistor to VSS permits a

power-on reset using only an external capacitor to V

CC. This pin is an

output when the hardware watchdog forces a system reset.

Table 4-1.

Pin Description (Continued)

Mnemonic

Pin Number

Type

Name and Function

PLCC44 VQFP44

PLCC68

VQFP64

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