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4115L–AERO–06/05

MG2RT

The MG2RT library allows straight forward migration from the MG1RT and MG1 Sea of Gates.

A netlist based on this library can be simulated as either MG2RT or MG2RTP. It can also be sim-

ulated as MG2 provided there are no SEU hardened cells.

Note:

Not available for new designs.

Libraries

The MG2RT cell library has been designed to take full advantage of the features offered by both

logic and test synthesis tools.

Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST

methodologies.

More complex macro functions are available in VHDL, such as Two-wire Interface (TWI), UART,

Timer.

Block Generators

Block generators are used to create a customer specific simulation model and metallisation pat-

tern for regular functions like RAM and DPRAM. The basic cell architecture allows one bit per

cell for RAM and DPRAM. The main characteristics of these generators are summarised below.

Table 1. List of Available MG2RT Matrices

Type

Total Gates

Typical Usable

Gates

Total Pads

Maximum

Programmable I/O

44616

31200

173

150

MG2091E

91464

64000

237

214

193800

135600

333

310

MG2265E

264375

185000

385

362

361680

253100

445

422

MG2480E

481143

336800

507

484

Function

Maximum

Size (bits)

Bits/Word

Typical Characteristics (16 Kbits) at 5V

Access Time (ns)

Used Cells

RAM

32K

1-36

8.6

20K

DPRAM

32K

1-36

9.2

23K