CS47048 Data Sheet

Audio SOC Processor Family

4

Copyright 2008 Cirrus Logic

DS787A7

5.17.2 Analog Output Characteristics (Automotive) ........................................................................ 28

5.17.3 Combined DAC Interpolation & On-chip Analog Filter Response ........................................ 29

6. Ordering Information ............................................................................................................30

7. Environmental, Manufacturing, & Handling Information ..................................................30

8. Device Pinout Diagram .........................................................................................................31

8.1 CS47048, 100-Pin LQFP Pinout Diagram ........................................................................................... 31

9. 100-pin LQFP with Exposed Pad Package Drawing .........................................................31

10. Parameter Definitions .........................................................................................................33

10.1 Dynamic Range ................................................................................................................................. 33

10.2 Total Harmonic Distortion + Noise ..................................................................................................... 33

10.3 Frequency Response ........................................................................................................................ 33

10.4 Interchannel Isolation ........................................................................................................................ 33

10.5 Interchannel Gain Mismatch .............................................................................................................. 33

10.6 Gain Error .......................................................................................................................................... 33

10.7 Gain Drift ........................................................................................................................................... 33

11. Revision History ..................................................................................................................33

Figures

Figure 1. CS47048 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 3. XTI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 4. Serial Control Port - SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 5. Serial Control Port - SPI Master Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6. Serial Control Port - I2C Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 7. Serial Control Port - I2C Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8. Digital Audio Input (DAI) Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9. Digital Audio Output Port Timing, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10. Digital Audio Output Port Timing, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11. ADC Single-Ended Input Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 12. ADC Differential Input Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 13. DAC Single-Ended Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 14. DAC Differential Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 15. Maximum Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 16. CS47048 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 17. 100-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32