CS42436-DMZ datasheet(9/61 Pages) CIRRUS

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DS647F2

CS42436

2. PIN DESCRIPTIONS - HARDWARE MODE

Pin Name

Pin Description

AIN5_MUX

AIN6_MUX

Analog Input Multiplexer

(Input) - Allows selection between the A and B single-ended inputs of

ADC3.

MFREQ

MCLK Frequency (Input) - Sets the required frequency range of the input Master Clock.

ADC3_HPF

ADC3 High-Pass Filter Freeze (Input) - When this pin is driven high, the internal high-pass filter

will be disabled for ADC3.The current DC offset value will be frozen and continue to be subtracted

from the conversion result.

RST

Reset (Input) - The device enters a low-power mode and all internal registers are reset to their

default settings when low.

VLC

Control Port Power (Input) - Determines the required signal level for the control port interface.

See “Digital I/O Pin Characteristics” on page 8.

Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format.

Digital Power (Input) - Positive power supply for the digital section.

DGND

9,18

Digital Ground (Input) - Ground reference for the digital section.

VLS

Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter-

faces. See “Digital I/O Pin Characteristics” on page 8.

SCLK

Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs.

MCLK

Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters.

ADC_SDOUT

ADC_SINGLE

Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data. Start-up

Option for Hardware Mode: Pull-up to VLS enables Single-Ended Mode for AIN5-AIN6.

DAC_SDIN

DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data.

AIN5_MUX

14 15 16 17 18 19 20 21 22 23 24 25

52 51 50 49 48 47 46 45 44 43 42 41

VLS

MCLK

VLC

ADC3_HPF

TSTO

AOUT5+

AGND

ADC_SDOUT/

ADC3_SINGLE

MFREQ

RST

AOUT6+

DGND

SCLK

AOUT6-

AIN6_MUX

AOUT5-

TSTO

AIN1+

AIN1-

CS42436

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