16

DS601F2

CS5340

Confidential Draft

3/11/08

4.2.1

Operation as a Clock Master

As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally de-

rived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as

shown in Figure 18.

4.2.2

Operation as a Clock Slave with Auto-Detect

LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be

synchronously derived from the master clock and must be equal to Fs. It is also recommended that the

serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system

performance.

A unique feature of the CS5340 is the automatic selection of either Single-, Double- or Quad-Speed mode

when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode

pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio

sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are

not supported when operating with a fast MCLK (512x, 256x, 128x for Single-, Double-, and Quad-Speed

Modes, respectively). Please refer to Table for supported sample rate ranges.

÷ 128

÷ 256

÷ 64

M0

M1

LRCK Output

(Equal to Fs)

Single

Speed

Quad

Speed

Double

Speed

00

01

10

÷ 2

÷ 4

÷ 1

SCLK Output

Single

Speed

Quad

Speed

Double

Speed

00

01

10

÷ 2

÷ 1

0

1

MCLK

Auto-Select

Figure 18. CS5340 Master Mode Clocking