DS861PP1

31

CS5346

7.3

ADC Control - Address 04h

7.3.1

Functional Mode (Bits 7:6)

Function:

Selects the required range of sample rates.

7.3.2

Digital Interface Format (Bit 4)

Function:

The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format

bit. The options are detailed in Table 7 and may be seen in Figure 3 and Figure 4.

7.3.3

Mute (Bit 2)

Function:

When this bit is set, the serial audio output of the both channels is muted.

7.3.4

High-Pass Filter Freeze (Bit 1)

Function:

When this bit is set, the internal high-pass filter is disabled.The current DC offset value will be frozen and

continue to be subtracted from the conversion result. See “High-Pass Filter and DC Offset Calibration” on

page 22.

7.3.5

Master / Slave Mode (Bit 0)

Function:

This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master

Mode, while clearing this bit selects Slave Mode.

7

6

5

432

10

FM1

FM0

Reserved

DIF

Reserved

Mute

HPFFreeze

M/S

FM1

FM0

Mode

0

0

Single-Speed Mode: 8 to 50 kHz sample rates

0

1

Double-Speed Mode: 50 to 100 kHz sample rates

1

0

Quad-Speed Mode: 100 to 200 kHz sample rates

11

Reserved

Table 6. Functional Mode Selection

DIF

Description

Format

Figure

0

Left-Justified (default)

0

3

1I²S

1

4

Table 7. Digital Interface Formats