CS4364 datasheet(28/50 Pages) CIRRUS

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DS619F1

CS4364

Figure 21. Recommended Mute Circuitry

4.12

Recommended Power-Up Sequence

4.12.1

Hardware Mode

Hold RST low until the power supplies and configuration pins are stable, and the master and left/right

clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the

registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.

If RST can not be held low long enough the SDINx pins should remain static low until all other clocks

are stable, and if possible the RST should be toggled low again once the system is stable.

Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the

Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024

LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).

4.12.2

Software Mode

Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the

appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default

settings, FILT+ will remain low, and VQ will be connected to VA/2.

Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in

Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-

Speed Mode).

In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the

completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-

Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be

loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1, then set the

format and mode control bits to the desired settings.

If more than the stated number of LRCK cycles passes before CPEN bit is written then the chip will

enter Hardware Mode and begin to operate with the M0-M4 as the mode settings. CPEN bit may be

written at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit

can not be set in time then the SDINx pins should remain static low (this way no audio data can be

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