CS3011

CS3012

12

DS597F5

The loop gain plot shown in Figure 17 illustrates

the unity gain configuration, and indicates how this

is modified when using the amplifier in a higher

gain configuration with compensation. If it is config-

ured for higher gain, for example, 60 dB, the x–axis

will move up by 60 dB (line B). Capacitor C2 adds

a zero and a pole. The modified plot indicates the

effects of introducing the pole and zero due to ca-

pacitor C2. The pole can be located at any fre-

quency higher than the hand-over frequency, the

zero has to be at a frequency lower than the hand-

over frequency so as to provide adequate gain

margin. The separation between the pole and the

zero is governed by the closed loop gain. The zero

cade and –80 dB/decade slopes. The point X in the

figure should be at closed loop gain plus 20 dB

gain margin. The value for C2 = 1/(2

πR1p1). Us-

ing p1 = 500 kHz works very well and is indepen-

dent of gain. As the closed loop gain is changed,

the zero location is also modified if R1 remains

fixed. Capacitor C2 can be increased in value to

limit the amplifier’s rising noise above 1 kHz.

-100 dB/dec

-80 dB/dec

z

1

p

1

Margin

-20 dB/dec

50kHz

1MHz

5MHz

Desired Closed

Loop Gain

X

FREQUENCY

B

Figure 17. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation

2.4 MHz

25 kHz

500 kHz