CS2000-CP

DS761PP1

15

time listed in the “AC Electrical Characteristics” on page 8 after which lock will be acquired and the PLL

output will resume.

have no effect and the PLL output will continue until CLK_IN is re-applied (see Figure 10). Once CLK_IN

is re-applied, the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT state will be

determined by the ClkOutUnl bit during this time.

continues while the PLL re-acquires lock (see Figure 11). When ClkSkipEn is disabled and CLK_IN is re-

moved the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only

for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl bit during this

time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will remain continuous

throughout the missing CLK_IN period including the time while the PLL re-acquires lock.

Referenced Control

Register Location

ClkSkipEn.............................. “Clock Skip Enable (ClkSkipEn)” on page 31

ClkOutUnl.............................. “Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 32

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=0

Lock Time

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=1

Lock Time

= invalid clocks

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=0

Lock Time

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=1

Lock Time

= invalid clocks

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=1

ClkOutUnl=0 or 1

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0

ClkOutUnl=1

Lock Time

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0

ClkOutUnl=0

Lock Time

= invalid clocks