CS42L55 datasheet(4/73 Pages) CIRRUS

4 / 73 page

DS773F1

CS42L55

5. REGISTER QUICK REFERENCE ........................................................................................................ 40

6. REGISTER DESCRIPTION .................................................................................................................. 42

6.1 Fab I.D. and Revision Register (Address 01h) (Read Only) ........................................................... 42

6.1.1 Chip Revision (Read Only) .................................................................................................... 42

6.2 Power Control 1 (Address 02h) ...................................................................................................... 42

6.2.1 Power Down ADC Charge Pump .......................................................................................... 42

6.2.2 Power Down ADC x ............................................................................................................... 42

6.2.3 Power Down .......................................................................................................................... 42

6.3 Power Control 2 (Address 03h) ...................................................................................................... 43

6.3.1 Headphone Power Control .................................................................................................... 43

6.3.2 Line Power Control ................................................................................................................ 43

6.4 Clocking Control 1 (Address 04h) ................................................................................................... 43

6.4.1 Master/Slave Mode ............................................................................................................... 43

6.4.2 SCLK Polarity ........................................................................................................................ 43

6.4.3 SCLK Equals MCLK .............................................................................................................. 44

6.4.4 MCLK Divide By 2 ................................................................................................................. 44

6.4.5 MCLK Disable ....................................................................................................................... 44

6.5 Clocking Control 2 (Address 05h) ................................................................................................... 44

6.5.1 Speed Mode .......................................................................................................................... 44

6.5.2 32 kHz Sample Rate Group ..................................................................................................45

6.5.3 Internal MCLK/LRCK Ratio ................................................................................................... 45

6.6 Class H Power Control (Address 06h) ............................................................................................ 45

6.6.1 Adaptive Power Adjustment .................................................................................................. 45

6.7 Miscellaneous Control (Address 07h) ............................................................................................. 45

6.7.1 Digital MUX ........................................................................................................................... 45

6.7.2 Analog Zero Cross ................................................................................................................ 46

6.7.3 Digital Soft Ramp .................................................................................................................. 46

6.7.4 Freeze Registers ................................................................................................................... 46

6.8 ADC, Line, HP MUX (Address 08h) ................................................................................................ 46

6.8.1 ADC x Input Select ................................................................................................................ 46

6.8.2 Line Input Select .................................................................................................................... 47

6.8.3 Headphone Input Select ........................................................................................................ 47

6.9 HPF Control (Address 09h) ............................................................................................................ 47

6.9.1 ADCx High-Pass Filter .......................................................................................................... 47

6.9.2 ADCx High-Pass Filter Freeze .............................................................................................. 47

6.9.3 HPF x Corner Frequency ...................................................................................................... 47

6.10 Misc. ADC Control (Address 0Ah) ................................................................................................ 48

6.10.1 ADC Channel B=A .............................................................................................................. 48

6.10.2 PGA Channel B=A .............................................................................................................. 48

6.10.3 Digital Sum .......................................................................................................................... 48

6.10.4 Invert ADC Signal Polarity ................................................................................................... 48

6.10.5 ADC Mute ............................................................................................................................ 48

6.11 PGA x MUX, Volume:

PGA A (Address 0Bh) & PGA B (Address 0Ch) ................................................................................... 49

6.11.1 Boostx ................................................................................................................................. 49

6.11.2 PGA x Input Select .............................................................................................................. 49

6.11.3 PGAx Volume ...................................................................................................................... 49

6.12 ADCx Attenuator Control:

ADCAATT (Address 0Dh) & ADCBATT (Address 0Eh) ....................................................................... 50

6.12.1 ADCx Volume ...................................................................................................................... 50

6.13 Playback Control 1 (Address 0Fh) ................................................................................................ 50

6.13.1 Power Down DSP ................................................................................................................ 50

6.13.2 HP/Line De-Emphasis ......................................................................................................... 50

6.13.3 Playback Channels B=A ...................................................................................................... 50

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