PCA9518AD datasheet(13/23 Pages) NXP

13 / 23 page

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

13 of 23

NXP Semiconductors

PCA9518A

Expandable 5-channel I2C-bus hub

10. Dynamic characteristics

[1]

For operation between published voltage ranges, refer to worst-case parameter in both ranges.

[2]

The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times are mostly internally controlled and are

only sensitive to load capacitance. The rise times are RC time constant controlled and therefor a speciﬁc numerical value can only be

given for ﬁxed RC time constants.

[3]

The SDA HIGH to LOW propagation delay includes the fall time from VDD to 0.5VDD of the EXPSDA1 or EXPSCL1 pins and the SDA or

SCL fall time from the quiescent HIGH (usually VDD) to below 0.3VDD. The SDA and SCL outputs have edge rate control circuits

included which make the fall time almost independent of load capacitance.

[4]

The SDA or SCL LOW to HIGH propagation delay includes the rise time constant from the quiescent LOW to 0.5VDD for the EXPSDA1

or EXPSCL2, the rise time constant for the quiescent LOW to 0.5VDD for the EXPSDA1 or EXPSCL1, and the rise time constant from

the quiescent external driven LOW to 0.7VDD for the SDA or SCL output. All of these rise times are RC time constants determined by the

external resistance and total capacitance for the various nodes.

Table 6.

Dynamic characteristics

VDD = 3.0 V to 3.6 V[1]; VSS =0V; Tamb = −40 °Cto+85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tPHL

HIGH to LOW propagation delay

SDA to SDAn, or

SCL to SCLn; Figure 7

[2][3] 105

202

389

tPLH

LOW to HIGH propagation delay

SDA to SDAn, or

SCL to SCLn; Figure 7

[2][4] 110

259

265

tPHL1

HIGH to LOW propagation delay 1

EXPSDA1 to SDA, or

EXPSCL1 to SCL; Figure 7

109

193

327

tPLH1

LOW to HIGH propagation delay 1

EXPSDA1 to SDA, or

EXPSCL1 to SCL; Figure 7

130

153

179

tPLH2

LOW to HIGH propagation delay 2

EXPSDA2 to SDA, or

EXPSCL2 to SCL; Figure 7

160

234

279

tTHL

HIGH to LOW output transition time

SDA, SCL; Figure 7

110

187

tTLH

LOW to HIGH output transition time

SDA, SCL; Figure 7

0.85 RC

tsu

set-up time

enable to START condition

300

hold time

enable after STOP condition

300

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