LPC2387_3

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 — 29 October 2008

13 of 52

NXP Semiconductors

LPC2387

Single-chip 16-bit/32-bit microcontroller

[1]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input,

digital section of the pad is disabled.

[3]

5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,

digital section of the pad is disabled.

[4]

Open-drain configuration applies to all functions on this pin.

[5]

Pad provides digital I/O and USB functions. It is designed in accordance with the

USB specification, revision 2.0 (Full-speed and

Low-speed mode only).

[6]

5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis

[7]

5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis

[8]

Pad provides special analog functionality.

[9]

Pad provides special analog functionality.

[10] Pad provides special analog functionality.

[11] Pad provides special analog functionality.

[12] Pad provides special analog functionality.

[13] Pad provides special analog functionality.

7.

Functional description

7.1 Architectural overview

The LPC2387 microcontroller consists of an ARM7TDMI-S CPU with emulation support,

the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip

memory, the AMBA AHB interfacing to high-speed on-chip peripherals, and the AMBA

APB for connection to other on-chip peripheral functions. The microcontroller permanently

configures the ARM7TDMI-S processor for little-endian byte order.

The LPC2387 implements two AHB in order to allow the Ethernet block to operate without

interference caused by other system activity. The primary AHB, referred to as AHB1,

includes the VIC and GPDMA controller.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,

and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2

are the ARM7 and the Ethernet block.

10[13]

I

analog 3.3 V pad supply voltage: This should be nominally the same voltage

used to power the ADC and DAC.

VREF

12[13]

I

should be isolated to minimize noise and error. Level on this pin is used as a

reference for ADC and DAC.

VBAT

19[13]

I

RTC pin power supply: 3.3 V on this pin supplies the power to the RTC

peripheral.

Table 3.

Symbol

Pin

Type

Description