LPC2157 datasheet(21/45 Pages) NXP

21 / 45 page

LPC2157_2158_1

Product data sheet

Rev. 01 — 15 October 2008

21 of 45

NXP Semiconductors

LPC2157/2158

Single-chip 16-bit/32-bit microcontrollers

slave can communicate on the bus during a given data transfer. The SSP supports full

duplex transfers, with data frames of 4 bits to 16 bits of data ﬂowing from the master to the

slave and from the slave to the master. Often only one of these data ﬂows carries

meaningful data.

6.14.1 Features

• Compatible with Motorola’s SPI, TI’s 4-wire SSI and National Semiconductor’s

Microwire buses.

• Synchronous serial communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four bits to 16 bits per frame.

6.15 General purpose timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

The LPC2157/2158 can count external events on one of the capture inputs if the minimum

external pulse is equal or longer than a period of the PCLK. In this conﬁguration, unused

capture lines can be selected as regular timer capture inputs, or used as external

interrupts.

6.15.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• External event counter or timer operation.

• Four 32-bit capture channels per timer/counter that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

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