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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TS68HC901CP5 датащи(PDF) 16 Page - STMicroelectronics |
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TS68HC901CP5 датащи(HTML) 16 Page - STMicroelectronics |
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16 / 42 page  7 ACTIVE EDGE REGISTER 0 AER (03h) GPIP7 GPIP6 GPIP5 GPIP4 GPIP3 GPIP2 GPIP1 GPIP0 1 = RISING 2 = FALLING DATA DIRECTION REGISTER DDR (05h) GPIP7 GPIP6 GPIP5 GPIP4 GPIP3 GPIP2 GPIP1 GPIP0 1 = OUTPUT 2 = INPUT GENERAL PURPOSE I/O DATA REGISTER GPIP (01h) GPIP7 GPIP6 GPIP5 GPIP4 GPIP3 GPIP2 GPIP1 GPIP0 Figure 11 : Note The transition detector is an exclusive-OR gate whose inputs are the edge bit and the input buffer. As a result, writing the EAR may cause an interrupt- producing transition, depending upon the state of the input. So, the AER should be configured before enabling interrupts via the interrupt enable registers (IERA and IERB). Also, changing the edge bit while interrupts are enabled may cause an interrupt on the corresponding channel. DATA DIRECTION REGISTER The data direction register (DDR) allows the pro- grammer to define I0 through I7 as inputs or outputs by writing the corresponding bit. When a bit of the data direction register is written as a zero, the cor- responding interrupt I/O pin will be a high-impe- dance input. Writing a one to any bit of the data di- rection register will cause the corresponding pin to be configured as a push-pull output. ® TS68HC901 16/42 |
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