DS3102_08 datasheet(2/141 Pages) MAXIM

2 / 141 page

____________________________________________________________________________________________ DS3102

Rev: 102808

2 of 141

Table of Contents

STANDARDS COMPLIANCE ..........................................................................................................6

APPLICATION EXAMPLE ...............................................................................................................7

BLOCK DIAGRAM...........................................................................................................................8

DETAILED DESCRIPTION ..............................................................................................................9

DETAILED FEATURES .................................................................................................................11

5.1

INPUT CLOCK FEATURES ...............................................................................................................11

5.2

T0 DPLL FEATURES .....................................................................................................................11

5.3

T4 DPLL FEATURES .....................................................................................................................11

5.4

OUTPUT APLL FEATURES .............................................................................................................12

5.5

OUTPUT CLOCK FEATURES............................................................................................................12

5.6

REDUNDANCY FEATURES ..............................................................................................................12

5.7

GENERAL FEATURES .....................................................................................................................12

PIN DESCRIPTIONS......................................................................................................................13

FUNCTIONAL DESCRIPTION .......................................................................................................17

7.1

OVERVIEW ....................................................................................................................................17

7.2

DEVICE IDENTIFICATION AND PROTECTION .....................................................................................18

7.3

LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION.............................................................18

7.4

INPUT CLOCK CONFIGURATION ......................................................................................................19

7.4.1

Signal Format Configuration ................................................................................................................ 19

7.4.2

Frequency Configuration...................................................................................................................... 20

7.5

INPUT CLOCK MONITORING............................................................................................................21

7.5.1

Frequency Monitoring .......................................................................................................................... 21

7.5.2

Activity Monitoring ................................................................................................................................ 21

7.5.3

Selected Reference Activity Monitoring ............................................................................................... 22

7.6

INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING....................................................................23

7.6.1

Priority Configuration............................................................................................................................ 23

7.6.2

Automatic Selection Algorithm ............................................................................................................. 23

7.6.3

Forced Selection .................................................................................................................................. 24

7.6.4

Ultra-Fast Reference Switching ........................................................................................................... 24

7.6.5

External Reference Switching Mode.................................................................................................... 24

7.6.6

Output Clock Phase Continuity During Reference Switching .............................................................. 25

7.7

DPLL ARCHITECTURE AND CONFIGURATION ..................................................................................26

7.7.1

T0 DPLL State Machine....................................................................................................................... 27

7.7.2

T4 DPLL State Machine....................................................................................................................... 30

7.7.3

Bandwidth ............................................................................................................................................ 32

7.7.4

Damping Factor.................................................................................................................................... 32

7.7.5

Phase Detectors................................................................................................................................... 32

7.7.6

Loss-of-Lock Detection ........................................................................................................................ 33

7.7.7

Phase Build-Out ................................................................................................................................... 34

7.7.8

Input to Output (Manual) Phase Adjustment........................................................................................ 34

7.7.9

Phase Recalibration ............................................................................................................................. 34

7.7.10

Frequency and Phase Measurement................................................................................................... 35

7.7.11

Input Jitter and Wander Tolerance....................................................................................................... 36

7.7.12

Jitter and Wander Transfer .................................................................................................................. 36

7.7.13

Output Jitter and Wander..................................................................................................................... 37

7.8

OUTPUT CLOCK CONFIGURATION...................................................................................................37

7.8.1

Signal Format Configuration ................................................................................................................ 38

7.8.2

Frequency Configuration...................................................................................................................... 38

7.9

EQUIPMENT REDUNDANCY CONFIGURATION...................................................................................45

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