ADV3201ASWZ datasheet(29/36 Pages) AD

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ADV3200/ADV3201

Rev. 0 | Page 29 of

APPLICATIONS INFORMATION

PROGRAMMING

The ADV3200/ADV3201 are programmed serially through a

193-bit serial word that updates the matrix and the state of the

sync-tip clamps each time the part is programmed.

Serial Programming Description

The serial programming mode uses the CLK, DATA IN,

UPDATE, and CS device pins. The first step is to assert a low

on CS to select the device for programming. The UPDATE

signal should be high during the time that data is shifted into

the serial port of the device. If UPDATE is low, the data is still

shifted in, and the transparent, asynchronous latches allow the

data to reach the matrix. This causes the matrix to try to update

itself to every intermediate state defined by the shifted-in data.

The data at DATA IN is clocked in at every rising edge of CLK.

A total of 193 bits must be shifted in to complete the program-

ming. For each of the 32 outputs, there are five bits (D4 to D0)

that determine the source of its input followed by one bit (D5)

that determines the enabled state of the output. If D5 is low

(output disabled), the five associated bits (D4 to D0) do not

matter because no input is switched to that output.

The first bit shifted into the logic is used to enable or disable

the sync-tip clamps. If this bit is low, the sync-tip clamps are

disabled; otherwise, they are enabled.

The sync-tip clamp bit is shifted in first, followed by the most

significant output address data (OUT31). The enable bit (D5) is

shifted in first, followed by the input address (D4 to D0) entered

sequentially with D4 first and D0 last. Each remaining output is

programmed sequentially, until the least significant output

address data is shifted in. At this point, UPDATE can be taken

low, which causes the device to be programmed according to

the data that was just shifted in. The second-rank latches are

asynchronous and, when UPDATE is low, they are transparent.

If more than one ADV3200/ADV3201 device is to be serially

programmed in a system, the DATA OUT signal from one

device can be connected to the DATA IN of the next device to

form a serial chain. All of the CLK and UPDATE pins should be

connected in parallel and operated as described previously. The

serial data is input to the DATA IN pin of the first device of the

chain, and it ripples through to the last. Therefore, the data for

the last device in the chain should come at the beginning of the

programming sequence. The length of the programming sequence

is 193 bits multiplied by the number of devices in the chain.

Reset

When powering up the ADV3200/ADV3201, it is usually

desirable to have the outputs come up in the disabled state. The

RESET pin, when taken low, causes all outputs to be disabled.

After power-up, the UPDATE pin should be driven high prior

to raising RESET.

Because the data in the shift register is random after power-up,

it should not be used to program the matrix, or the matrix can

enter unknown states. To prevent this, do not apply a logic low

signal to UPDATE initially after power-up. The shift register

should first be loaded with the desired data, and then UPDATE

can be taken low to program the device.

The RESET pin has a 25 kΩ pull-up resistor to DVCC that can

be used to create a simple power-on reset circuit. A capacitor

from RESET to ground holds RESET low for some time while

the rest of the device stabilizes. The low condition causes all the

outputs to be disabled. The capacitor then charges through the

pull-up resistor to the high state, thus allowing the full program-

ming capability of the device.

The CS pin has a 25 kΩ pull-down resistor to DGND.

AC COUPLING OF INPUTS

Using ac-coupled inputs presents a challenge for video systems

operating from low supply voltages or from a single 5 V supply.

In NTSC and PAL video systems, 700 mV is the approximate

difference between the maximum signal voltage and the black

level, assuming that sync has been stripped. However, as shown

in Figure 99, a dynamic range of twice the maximum signal

swing is required if the inputs are to be ac-coupled. A solution

to this extended requirement for dynamic range is the sync-tip

clamp feature.

+700mV

–700mV

+5V

GND

VAVG

VSIGNAL

VREF

WHITE LINE WITH BLACK PIXEL

BLACK LINE WITH WHITE PIXEL

VINPUT = VREF + VSIGNAL

VREF ~ VAVG

VREF IS A DC VOLTAGE

SET BY THE RESISTORS

Figure 99. Pathological Case for Input Dynamic Range

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