ADIS16300

Rev. 0 | Page 12 of 16

Restoring Factory Calibration

Set GLOB_CMD[1] = 1 (DIN = 0xBE02) to execute this function,

which resets each user calibration register (see Table 10 and

Table 11) to 0x0000, resets all sensor data to zero, and auto-

matically updates the flash memory (50 ms). See Table 12.

Linear Acceleration Bias Compensation (Gyroscope)

Set MSC_CTRL[7] = 1 (DIN = 0xB486) to enable correction for

low frequency acceleration influences on gyroscope bias. Note

that the DIN sequence also preserves the factory default condi-

tion for the data ready function (see Table 17).

OPERATIONAL CONTROL

Global Commands

The GLOB_CMD register provides trigger bits for several useful

functions. Setting the assigned bit to 1 starts each operation,

which returns to the bit to 0 after completion. For example, set

GLOB_CMD[7] = 1 (DIN = 0xBE80) to execute a software

reset, which stops the sensor operation and runs the device

through its start-up sequence. This includes loading the control

registers with their respective flash memory locations prior to

producing new data. Reading the GLOB_CMD registers (DIN =

0x3E00) starts the burst mode read sequence.

Table 12. GLOB_CMD

Bits

Description

[15:8]

Not used

[7]

Software reset command

[6:5]

Not used

[4]

Precision autonull command

[3]

Flash update command

[2]

Auxiliary DAC data latch

[1]

Factory calibration restore command

[0]

Autonull command

Internal Sample Rate

The ADIS16300 performs best when the sample rate is set to the

factory default setting of 819.2 SPS. For applications that value

lower sample rates, the SMPL_PRD register controls the

ADIS16300 internal sample (see Table 13), and the following

relationship produces the sample rate:

Table 13. SMPL_PRD

Bit

Description

[15:8]

Not used

[7]

0 = 0.61035 ms, 1 = 18.921 ms

[6:0]

For example, set SMPL_PRD[7:0] = 0x0A (DIN = 0xB60A) for

an internal sample period of 6.7 ms (sample rate = 149 SPS).

For systems that value lower sample rates, in-system character-

ization can help determine performance trade-offs.

Power Management

Setting SMPL_PRD ≥ 0x0A also sets the sensor in low power

mode. In addition to sensor performance, this mode also affects

SPI data rates (see Table 2). Two sleep mode options are listed

in Table 14. Set SLP_CNT[8] = 1 (DIN = 0xBB01) to start the

indefinite sleep mode, which requires CS assertion (high to

low), reset, or power cycle to wake-up. Set SLP_CNT[7:0] =

0x64 (DIN = 0xBA64) to put the ADIS16300 to sleep for 100

seconds, as an example of the programmable sleep time option.

Table 14. SLP_CNT

Bit

Description

[15:9]

Not used

[8]

Indefinite sleep mode, set to 1

[7:0]

Programmable time bits, 0.5 sec/LSB

Digital Filtering

The signal conditioning circuit of each sensor has a typical

analog bandwidth of 350 Hz. A programmable Bartlett window

FIR filter provides an opportunity for additional noise reduction

on all output data registers. SENS_AVG[2:0] controls the

number of taps according to the equation in Table 15. For

example, set SENS_AVG[2:0] = 110 (DIN = 0xB806) to

establish a 129-tap setting.

0

–20

–40

–60

–80

–100

–120

–140

0.001

0.01

0.1

1

FREQUENCY (

N = 5

N = 9

N = 33

N = 129

Figure 15. Bartlett Window FIR Frequency Response