AD9714/AD9715/AD9716/AD9717

Rev. 0 | Page 39 of 48

Table 15. Timer Register List

Bit Name

Description

CLKMODEQ[1:0]

Q datapath retimer clock selected output. Valid after SEARCHING goes low.

Searching

High indicates the internal data path retimer is searching for clock relationship (DAC is not usable until it is low again).

Reacquire

Changing this bit from 0 to 1 causes the data path retimer circuit to reacquire the clock relationship.

CLKMODEN

0: Uses CLKMODEI/CLKMODEQ values (as computed by the two internal retimers) for I and Q clocking.

1: Uses CLKMODE value set in CLKMODEI[1:0] for both I and Q retimers (that is, force the retimer).

CLKMODEI[1:0]

I datapath retimer clock selected output. Valid after searching goes low.

If CLKMODEN = 1, a value written to this register overrides both I and Q automatic retimer values.

Table 16. CLKMODE Details

CLKMODEI[1:0]/CLKMODEQ[1:0]

DCLKIO-to-CLKIN Phase Relationship

RETIMER-CLK Selected

00

0° to 90°

Phase 2

01

90° to 180°

Phase 3

10

180° to 270°

Phase 3

11

270° to 360°

Phase 1

When reset is pulsed high and then returns low (the part is in

SPI mode), the retimer runs and automatically selects a suitable

clock phase for the RETIMER-CLK within 128 clock cycles. The

SPI searching bit returns to low, indicating that the retimer has

locked and the part is ready for use. The reacquire bit can be

used to reinitiate phase detection in the I and Q retimers at

any time. CLKMODEQ[1:0] and CLKMODEI[1:0] provide

readback for the values picked by the internal phase detectors

in the retimer (see Table 16).

To force the two retimers (I and Q) to pick a particular phase

for the retimer clock (they must both be forced to the same

value), CLKMODEN should be set high and the required phase

value is written into CLKMODEI[1:0] and CLKMODEQ[1:0].

For example, if the DCLKIO and the CLKIN are in phase to first

order, the user could safely force the retimers to pick Phase 2 for

the RETIMER-CLK. This forcing function may be useful for

synchronizing multiple devices.

In pin mode, it is expected that the user tie CLKIN and DCLKIO

together. The device has a small amount of programmable

functionality using the now unused SPI pins (SCLK, SDIO, and

CS). If the two chip clocks are tied together, the SCLK pin can

be tied to ground and the chip uses a clock for the retimer that

is 180° out of phase with the two input clocks (that is, Phase 2,

which is the safest or best option). The chip has an additional

option in pin mode when the redefined SCLK pin is high. Use

this mode if utilizing pin mode, but CLKIN and DCLKIO are

not tied together (that is, not in phase). Holding SCLK high

causes the internal clock detector to use the phase detector

output to determine which clock to use in the retimer (that is,

select a suitable RETIMER-CLK phase). The action of taking

SCLK high causes the internal phase detector to reexamine the

two clocks and determine the relative phase. Whenever the user

wants to reevaluate the relative phase of the two clocks, the

SCLK pin can be taken low and then high again.

ESTIMATING THE OVERALL DAC PIPELINE DELAY

DAC pipeline latency is affected by the phase of the RETIMER-

CLK that is selected. If latency is critical to the system and needs

to be constant, the retimer should be forced to a particular phase

and not be allowed to automatically select a phase each time.

Consider the case when DCLKIO = CLKIN (that is, in phase),

and the RETIMER-CLK is forced to Phase 2. Assume that

IRISING is 1 (that is, I data is latched on the rising edge and

Q data on the falling edge). Then the latency to the output for

the I-channel is 3 clock cycles (D-FF (1), D-FF (3), and D-FF

(4), but not D-FF (2) because it is latched on the half clock

cycle or 180°). The latency to the output for the Q-channel

from the time the falling edge latches it at the pads in D-FF (0)

is 2.5 clock cycles (½ clock cycle to D-FF (1), 1 clock cycle to

D-FF (3), and 1 clock cycle to D-FF (4)). This latency for the

AD9714/AD9715/ AD9716/AD9717 is case specific and needs

to be calculated based on the RETIMER-CLK phase that is

automatically selected or manually forced.