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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9520-0/PCBZ датащи(PDF) 11 Page - Analog Devices |
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AD9520-0/PCBZ датащи(HTML) 11 Page - Analog Devices |
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11 / 84 page  AD9520-0 Rev. 0 | Page 11 of 84 CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL ABSOLUTE PHASE NOISE Internal VCO; direct-to-LVPECL output and for loop bandwidths < 1 kHz VCO = 2.95 GHz; Output = 2.95 GHz @ 1 kHz Offset −46 dBc/Hz @ 10 kHz Offset −78 dBc/Hz @ 100 kHz Offset −104 dBc/Hz @ 1 MHz Offset −123 dBc/Hz @ 10 MHz Offset −139 dBc/Hz @ 40 MHz Offset −145 dBc/Hz VCO = 2.75 GHz; Output = 2.75 GHz @ 1 kHz Offset −49 dBc/Hz @ 10 kHz Offset −80 dBc/Hz @ 100 kHz Offset −106 dBc/Hz @ 1 MHz Offset −125 dBc/Hz @ 10 MHz Offset −140 dBc/Hz @ 40 MHz Offset −146 dBc/Hz VCO = 2.55 GHz; Output = 2.55 GHz @ 1 kHz Offset −51 dBc/Hz @ 10 kHz Offset −82 dBc/Hz @ 100 kHz Offset −108 dBc/Hz @ 1 MHz Offset −127 dBc/Hz @ 10 MHz Offset −140 dBc/Hz @ 40 MHz Offset −146 dBc/Hz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup where the reference source is clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R DIV = 1 VCO = 2.949 GHz; LVPECL = 245.76 MHz; PLL LBW = 63 kHz 176 fs rms Integration BW = 200 kHz to 10 MHz 351 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.703 GHz; LVPECL = 122.88 MHz; PLL LBW = 63 kHz 158 fs rms Integration BW = 200 kHz to 10 MHz 324 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.703 GHz; LVPECL = 61.44 MHz; PLL LBW = 63 kHz 177 fs rms Integration BW = 200 kHz to 10 MHz 330 fs rms Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup where the reference source is jittery, so a narrower PLL loop bandwidth is used; reference = 19.44 MHz; R DIV = 162 VCO = 2.799 GHz; LVPECL = 155.52 MHz; PLL LBW = 1.8 kHz 652 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.703 GHz; LVPECL = 122.88 MHz; PLL LBW = 2.1 kHz 607 fs rms Integration BW = 12 kHz to 20 MHz |
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