AD7699BCPZ datasheet(5/28 Pages) AD

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AD7699

Rev. 0 | Page 5 of 28

TIMING SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VREF = 4.096 to VDD, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter1

Symbol

Min

Typ

Max

Unit

Conversion Time: CNV Rising Edge to Data Available

CONV

1.6

µs

Acquisition Time

ACQ

400

Time Between Conversions

CYC

µs

CNV Pulse Width

CNVH

Data Write/Read During Conversion

DATA

1.2

µs

SCK Period

SCK

DSDO + 2

SCK Low Time

SCKL

SCK High Time

SCKH

SCK Falling Edge to Data Remains Valid

HSDO

SCK Falling Edge to Data Valid Delay

DSDO

VIO Above 4.5 V

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV Low to SDO D15 MSB Valid

VIO Above 4.5 V

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV High or Last SCK Falling Edge to SDO High Impedance

DIS

CNV Low to SCK Rising Edge

CLSCK

DIN Valid Setup Time from SCK Falling Edge

SDIN

DIN Valid Hold Time from SCK Falling Edge

HDIN

1 See Figure 2 and Figure 3 for load conditions.

IOL

500µA

IOH

1.4V

TO SDO

50pF

Figure 2. Load Circuit for Digital Interface Timing

30% VIO

70% VIO

2V OR VIO – 0.5V1

0.8V OR 0.5V2

2V OR VIO – 0.5V1

tDELAY

1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 3. Voltage Levels for Timing

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