AD7699 datasheet(24/28 Pages) AD

24 / 28 page

AD7682/AD7689

Rev. 0 | Page 24 of 28

READ/WRITE SPANNING CONVERSION WITHOUT

A BUSY INDICATOR

This mode is used when the AD7682/AD7689 are connected to

any host using an SPI, serial port, or FPGA. The connection

diagram is shown in Figure 34, and the corresponding timing is

given in Figure 35. For SPI, the host should use CPHA = CPOL

= 0. Reading/writing spanning conversion is shown, which

covers all three modes detailed in the Digital Interface section.

A rising edge on CNV initiates a conversion, forces SDO to

high impedance, and ignores data present on DIN. After a

conversion is initiated, it continues until completion

irrespective of the state of CNV. CNV must be returned high

before the safe data transfer time, tDATA, and then held high

beyond the conversion time, tCONV, to avoid generation of the

busy signal indicator.

After the conversion is complete, the AD7682/AD7689 enter

the acquisition phase and power down. When the host brings

CNV low after tCONV (max), the MSB is enabled on SDO. The

host also must enable the MSB of CFG at this time (if necessary)

to begin the CFG update. While CNV is low, both a CFG

update and a data readback take place. The first 14 SCK rising

edges are used to update the CFG, and the first 15 SCK falling

edges clock out the conversion results starting with MSB − 1.

The restriction for both configuring and reading is that they

both occur before the tDATA time of the next conversion elapses.

All 14 bits of CFG[13:0] must be written, or they are ignored. In

addition, if the 16-bit conversion result is not read back before

tDATA elapses, it is lost.

The SDO data is valid on both SCK edges. Although the rising

edge can be used to capture the data, a digital host using the

SCK falling edge allows a faster reading rate, provided it has an

acceptable hold time. After the 16th (or 30th) SCK falling edge, or

when CNV goes high (whichever occurs first), SDO returns to

high impedance. If CFG readback is enabled, the CFG associ-

ated with the conversion result (n − 1) is read back MSB first

following the LSB of the conversion result. A total of 30 SCK

falling edges is required to return SDO to high impedance if

this is enabled.

MISO

MOSI

SCK

CNV

FOR SPI USE CPHA = 0, CPOL = 0.

SCK

SDO

DIN

AD7682/

AD7689

DIGITAL HOST

Figure 34. Connection Diagram for the AD7682/AD7689 Without a Busy Indicator

UPDATE (n)

CFG/SDO

UPDATE (n + 1)

CFG/SDO

ACQUISITION (n)

ACQUISITION

(n + 1)

ACQUISITION

(n - 1)

MSB MSB – 1

BEGIN DATA (n – 1)

BEGIN CFG (n + 1)

CFG

MSB

CFG

MSB – 1

LSB + 1

SEE NOTE

NOTES:

1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF

15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.

29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.

ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.

16/

CONVERSION (n)

RETURN CNV HIGH

FOR NO BUSY

END DATA (n – 1)

END CFG (n + 1)

CFG

LSB

tCONV

LSB

SCK

CNV

DIN

SDO

LSB + 1

16/

CONVERSION (n – 1)

RETURN CNV HIGH

FOR NO BUSY

END DATA (n – 2)

END CFG (n)

CFG

LSB

tCONV

tDATA

tCNVH

tDATA

tDIS

tEN

DSDO

HSDO

tHDIN

tSDIN

tCLSCK

DIS

tCONV

LSB

tACQ

CYC

(QUIET

TIME)

(QUIET

TIME)

Figure 35. Serial Interface Timing for the AD7682/AD7689 Without a Busy Indicator

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