AD5752BREZ datasheet(19/32 Pages) AD

19 / 32 page

AD5722/AD5732/AD5752

Rev. 0 | Page 19 of 32

Standalone Operation

The serial interface works with both a continuous and noncon-

tinuous serial clock. A continuous SCLK source can be used

only if SYNC is held low for the correct number of clock cycles.

In gated clock mode, a burst clock containing the exact number

of clock cycles must be used, and SYNC must be taken high

after the final clock to latch the data. The first falling edge of

SYNC starts the write cycle. Exactly 24 falling clock edges must

be applied to SCLK before SYNC is brought high again. If

SYNC is brought high before the 24th falling SCLK edge, the

data written is invalid. If more than 24 falling SCLK edges are

applied before SYNC is brought high, the input data is also

invalid. The input register addressed is updated on the rising

edge of SYNC. For another serial transfer to take place, SYNC

must be brought low again. After the end of the serial data

transfer, data is automatically transferred from the input shift

When the data has been transferred into the chosen register of

the addressed DAC, all DAC registers and outputs can be

updated by taking LDAC low while

*ADDITIONAL PINS OMITTED FOR CLARITY.

68HC11*

MISO

SDIN

SCLK

MOSI

SCK

PC7

PC6

SDO

SCLK

SDO

SCLK

SDO

SDIN

SYNC

LDAC

AD5722/

AD5732/

AD5752*

AD5722/

AD5732/

AD5752*

AD5722/

AD5732/

AD5752*

SYNC is high.

Figure 40. Daisy Chaining the AD5722/AD5732/AD5752

Daisy-Chain Operation

For systems that contain several devices, the SDO pin can be

used to daisy-chain several devices together. Daisy-chain mode

can be useful in system diagnostics and in reducing the number

of serial interface lines. The first falling edge of SYNC starts the

write cycle. SCLK is continuously applied to the input shift

applied, the data ripples out of the shift register and appears on

the SDO line. This data is clocked out on the rising edge of

SCLK and is valid on the falling edge. By connecting the SDO

of the first device to the SDIN input of the next device in the

chain, a multidevice interface is constructed. Each device in the

system requires 24 clock pulses. Therefore, the total number of

clock cycles must equal 24 × N, where N is the total number of

AD5722/AD5732/AD5752 devices in the chain. When the serial

transfer to all devices is complete, SYNC is taken high. This

latches the input data in each device in the daisy chain and

prevents any further data from being clocked into the input shift

A continuous SCLK source can only be used if SYNC is held

low for the correct number of clock cycles. In gated clock mode,

a burst clock containing the exact number of clock cycles must

be used, and SYNC

Readback Operation

must be taken high after the final clock to

latch the data.

Readback mode is invoked by setting the R/W bit = 1 in the

write operation to the serial input shift register. (If the SDO

output is disabled via the SDO disable bit in the control register,

it is automatically enabled for the duration of the read operation,

after which it is disabled again.) With R/

Figure 4

W = 1, Bit A2 to Bit A0,

in association with Bit REG2 to Bit REG0, select the register to

be read. The remaining data bits in the write sequence are don’t

care bits. During the next SPI write, the data appearing on the SDO

output contains the data from the previously addressed register.

For a read of a single register, the NOP command can be used in

clocking out the data from the selected register on SDO. The

readback diagram in

shows the readback sequence.

For example, to read back the DAC register of Channel A, the

following sequence should be implemented:

1. Write 0x800000 to the AD5722/AD5732/AD5752 input

DAC register of Channel A selected. Note that all the data

bits, DB15 to DB0, are don’t care bits.

2. Follow this with a second write, a NOP condition, 0x180000.

During this write, the data from the register is clocked out

on the SDO line.

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