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AD5590BBC датащи(PDF) 10 Page - Analog Devices

номер детали AD5590BBC
подробное описание детали  16 Input, 16 Output Analog I/O Port with Integrated Amplifiers
PDF  44 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD5590BBC датащи(HTML) 10 Page - Analog Devices

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AD5590
Rev. 0 | Page 10 of 44
DAC Timing Characteristics
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4.
DACVDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 6.
Parameter1
Limit at TMIN, TMAX; DACVDD = 2.7 V to 5.5 V
Unit
Conditions/Comments
t12
20
ns min
DSCLK cycle time
t2
8
ns min
DSCLK high time
t3
8
ns min
DSCLK low time
t4
13
ns min
DSYNC to DSCLK falling edge setup time
t5
4
ns min
Data setup time
t6
4
ns min
Data hold time
t7
0
ns min
DSCLK falling edge to DSYNC rising edge
t8
15
ns min
Minimum DSYNC high time
t9
13
ns min
DSYNC rising edge to DSCLK fall ignore
t10
0
ns min
DSCLK falling edge to DSYNC fall ignore
t11
10
ns min
LDAC pulse width low
t12
15
ns min
DSCLK falling edge to LDAC rising edge
t13
5
ns min
CLR pulse width low
t14
0
ns min
DSCLK falling edge to LDAC falling edge
t15
300
ns typ
CLR pulse activation time
1 Sample tested at 25°C to ensure compliance.
2 Maximum DSCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
t4
t3
DSCLK
DSYNCx
DDIN
t1
t2
t5
t6
t7
t8
DB31
t9
t10
t11
t12
LDAC1
LDAC2
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
CLR
t13
t15
VOUTx
DB0
Figure 4. DAC Timing Characteristics



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