AD5522JSVUZ datasheet(12/60 Pages) AD

12 / 60 page

AD5522

Rev. A | Page 12 of 60

Parameter 1, 2, 3

DVCC, Limit at TMIN, TMAX

Unit

Description

2.3 V to 2.7 V

2.7 V to 3.6 V

4.5 V to 5.25 V

t16

1.8

1.2

0.9

ns min

RESET pulse width low

t17

670

700

750

μs max

RESET time indicated by BUSY low

t18

400

ns min

Minimum SYNC high time in readback mode

t195, 6

ns max

SCLK rising edge to SDO valid; DVCC = 5 V to 5.25 V

1 Guaranteed by design and characterization; not production tested.

2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3 See Figure 5 and Figure 6.

4 Writes to more than one X1 register, engages the calibration engine for longer times, shown by the BUSY low time, t10. Subsequent writes to one or more X1 registers

should either be timed or should wait until BUSY returns high (see Figure 53). This is required to ensure data is not lost or overwritten.

5 t19 is measured with the load circuit shown in Figure 4.

6 SDO output slows with lower DVCC supply and may require use of a slower SCLK.

Table 3. LVDS Interface

DVCC, Limit at TMIN, TMAX

Parameter1, 2, 3

2.7 V to 3.6 V

4.5 V to 5.25 V

Unit

Description

ns min

SCLK cycle time

ns min

SCLK pulse width high and low time

ns min

SYNC to SCLK setup time

ns min

Data setup time

ns min

Data hold time

ns min

SCLK to SYNC hold time

t74

ns min

SCLK rising edge to SDO valid

150

ns min

Minimum SYNC high time in write mode after X1

ns min

Minimum SYNC high time in write mode after any

other register write

400

ns min

Minimum SYNC high time in readback mode

1 Guaranteed by design and characterization; not production tested.

2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3 See Figure 7.

4 SDO output slows with lower DVCC supply and may require use of slower SCLK.

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